JPH0383127A - Decimal divider - Google Patents

Abstract

PURPOSE:To reduce the number of operation cycles to one at the time of the use of the 10-th power as the divisor by providing a circuit which selects the output of a decimal dividing circuit and that of a shift circuit by the output of a 10-th power detecting circuit. CONSTITUTION:A decimal divider consists of a decimal dividing circuit 3 which calculates a quotient and a remainder in accordance with given dividend and divisor, a 10-th power detecting circuit 6 which detects that the divisor is the 10-th power, a shift circuit 4 which shifts the dividend right in response to the divisor, and a circuit 7 which selects the output of the decimal dividing circuit 3 and the output of the shift circuit 4 by the output of the 10-th detecting circuit 6. The dividend and the divisor are held in registers 1 and 2 respectively; and when the divisor is the 10-th power, the dividend is shifted in the shifter 4 by several bits and the result is held in a register 8 through the selector 7 in the next cycle. Thus, the operation cycle is shortened when the divisor is the 10-th power.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a decimal divider for an information processing device.

In particular, it relates to a decimal divider when the divisor is a 100-act power.

[Conventional technology]

Conventionally, a method shown in the flowchart of FIG. 2 has been used to perform decimal division.

To explain the flow in Figure 2, the first step is 10
Convert the dividend (DD) and divisor (DB) in decimal notation to binary notation. Generally, decimal arithmetic is often used when high arithmetic precision is required, and its internal notation is performed in binary coded decimal notation (BCD) or the like, so the above-mentioned conversion work is required. For the next step and subsequent steps, basically subtract the divisor (Ds) from the dividend (DD), repeat the subtraction if the result is greater than the divisor, and end the process when the result becomes smaller than the divisor. As a result, the number of times the divisor is subtracted from the dividend is used as the quotient. Furthermore, as post-processing, the value expressed in binary at that time is converted into decimal notation, and this value is output as a quotient.

Remaining days below [Problem to be solved by the invention] According to the method described above, its execution cycle is:

Depending on the size of the dividend and divisor, including the numerical conversion process of around 2, it will take several tens of cycles or more.

Thus, decimal division has the disadvantage of requiring many execution cycles. However, when considering its contents, the number of execution cycles increases when the divisor is 10.

The present invention is an attempt to solve these problems of the conventional devices, and provides a decimal arithmetic unit that can shorten the operation cycle when the divisor is a power of 10.

[Means to solve the problem]

The decimal divider of the present invention includes a decimal divider circuit that calculates a quotient and a remainder from a given dividend and a divisor, and a decimal divider circuit that calculates a quotient and a remainder from a given dividend and a divisor, and a
a 100 power detection circuit that detects that it is a power of 0;
In response to said divisor.

and a circuit that selects the output of the decimal division circuit and the shift circuit based on the output of the power of 10 detection circuit.

〔Example〕

Next, two aspects of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Register 1 is a register that inputs and holds the dividend.

Register 2 is a register that inputs and holds a divisor. 1
The decimal division circuit 3 is a decimal division circuit that inputs the dividend and divisor expressed in decimal notation from registers 1 and 2, respectively, performs decimal division, and outputs the quotient in decimal notation. The process requires several tens of machine cycles. Shifter 4 inputs the dividend held in register 1,
This circuit outputs the input value by shifting the input digits to the right by the shift count number of the other input. The shift count generation circuit 5 is a circuit that inputs the divisor held in the register 2 and outputs a shift count. 1
The power of 0 detection circuit 6 is a circuit that inputs the divisor held in the register 2, determines whether the input value is a power of 10, and outputs the result. selector 7 is 10
It has a function of inputting the outputs from the base/divider circuit 5 and the shifter 5 and switching between them using the output of the power of 10 detection circuit 6. Register 8 holds the output of selector 7.

Before explaining the operation, the shift count generation circuit 5 and the power of 10 detection circuit 6 will be explained first. Figure 3 (1
) shows the relationship between the input and output values of the shift count generation circuit 5. Here, regardless of whether the input (divisor) is a power of 10 or not, the output is the number of "ONs" expressed in decimal from the lower digits of the input.
) It shows the relationship between the input and output values of the curtain riding detection circuit B of ldlO. Here, it is determined whether the input (divisor) is equal to or less than 10, and the result is output.

Next, the overall operation of 2 will be explained.

First, a dividend and a divisor are held in register 1 and register 2, respectively. If the divisor is a power of 10, the shifter 4 shifts the dividend by several bits and the result is held in the register 8 through the selector 7 in the next cycle. On the other hand, if the divisor is not a multiplication of 10, the result of the operation of the decimal division circuit 5 according to the conventional method is stored in the register 8 through the selector 7 after several tens of cycles. Input for these cases.

The output pattern is shown in Figure 4 (all in decimal notation).

〔Effect of the invention〕

As described above, the present invention includes, in addition to the decimal division circuit, a 10 curtain multiplication detection circuit that detects that the divisor is a power of 10, and a shifter that shifts the dividend to the right in response to the divisor. with the circuit.

By providing a circuit that selects the output of the decimal division circuit and the shift circuit based on the output of the 10 curtain multiplication detection circuit, when the divisor is a curtain multiplication of 10, the calculation cycle can be reduced to 1.
This has the effect of shortening the cycle.

remainder 0

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a flowchart showing an example of a conventional method, and FIG. 3 shows the shift count generation circuit and 10 in FIG. FIG. 3 is an explanatory diagram of the input/output relationship of the curtain riding detection circuit. FIG. 4 is an explanatory diagram of the operation when the configuration of FIG. 1 is used. Explanation of symbols 21, 2...Register, 3...Decimal division circuit, 4...Shifter, 5...Shift count generation circuit, 6...10 curtain multiplication detection circuit, 7...・Selector, 8...Register. Figure 1 Figure 2 Figure 3 (1) (2)

Claims (1)

[Claims] 1. In an information processing device having a decimal division instruction, a decimal division circuit that calculates a quotient and a remainder from a given dividend and divisor, and a power of 10 detection that detects that the divisor is a power of 10. a shift circuit that shifts the dividend to the right in response to the divisor, and a circuit that selects the output of the decimal division circuit and the shift circuit based on the output of the power of 10 detection circuit. Characteristic decimal divider.