JPH02212927A - Binary integer multiplication processing method - Google Patents

Abstract

PURPOSE:To realize 63-bit integer type multiplication without using a floating decimal point instruction by executing sorting by means of the high-order n bits of the multiplicands and the high-order n bits of the multiplier, and when overflow does not occur, calculating the product between the multiplicand and multiplier by means of the calculation between the respective data at n bits. CONSTITUTION:When a multiplicand X is multiplied by a multiplier Y so that a multiplication result may be expressed in the range of 2n bits by a computer 10 whose one word consists of the n bits, first the multiplicand and multiplier are respectively divided into n bits in a processing stage P1. In a processing stage P2, the top bit of the low-order n bits is transferred to the lowest-order bit of the high-order n bits. The original value of the high-order n bits are shifted to a left side by one bit respectively. Next in a processing stage P3, the overflow is checked so that the multiplication result may be expressed in the range of 2n bits, and the product and sum of the respective n bits are calculated, and the calculation result is obtained. Thus the 63-bit integer type multiplication in a FORTRAN program, etc., can be realized without using the floating decimal point instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to a binary integer multiplication processing method that performs multiplication of a multiplicand and a multiplier whose length is twice the length of a binary integer handled by a multiplication instruction execution mechanism of a computer.

The purpose of this invention is to provide a means for implementing 63-bit integer type multiplication in FORTRAN programs, etc., without using floating point instructions.

The process of dividing each of the multiplicand , shift the upper n bits to the left by 1 bit, and shift the lower n bits to the left by 1 bit, and
A processing process in which the most significant bit of the bit is carried into the least significant bit of the upper n bits, and one case is divided according to the values of the upper n bits of the multiplicand X and the upper n bits of the multiplier Y,
The present invention is configured to include a process of detecting an overflow and, if an overflow does not occur, calculating the product of the multiplicand X and the multiplier Y by calculation between each n-bit data.

[Industrial application field]

The present invention relates to a binary integer multiplication processing method for multiplying a multiplicand and a multiplier whose length is twice the length of a two-way integer handled by a multiplication instruction execution mechanism of a computer.

In scientific and technical calculations and office processing calculations using computers.

Multiplication is frequently used. The simplest form of numbers handled by computers is a binary integer, but 2 is the number that can be multiplied by 1.
It is desired to increase the number of digits by one for a multiplicand expressed as a base integer.

[Conventional technology]

Conventionally, on FORTRAN Pro TR executed by a 18832-bit computer, multiplication of 31-bit integer types was possible, but multiplication of 63-bit integer types was not possible.

[Problem to be solved by the invention]

Conventionally, in FORTRAN Pro TR, etc., multiplication of 63-bit integer types was not possible, so when performing such multiplication, for example, convert an integer type value to a floating point number,
There was a problem in that after performing multiplication using floating point instructions, it was necessary to convert the result to an integer type. Therefore, the two processing procedures are complicated,
There was also the problem that processing was slow.

The present invention aims to solve the above-mentioned problems and provides a means for realizing 63-bit integer type multiplication in FORTRAN Pro TR etc. without using floating point instructions.

[Means to solve the problem]

FIG. 1 shows an example of the configuration of the present invention.

In FIG. 1, 10 represents a total of X machines consisting of a CPU, memory, etc., PI to R3 represent processing steps for multiplication by a computer IO, X represents a multiplicand, Y represents a multiplier, and R1 to R4 represent registers.

The computer IO has a plurality of registers R1 to R4 that hold n-bit data, and has a binary integer multiplication instruction execution mechanism set in these registers.

When performing multiplication by a multiplicand X and a multiplier Y, which are binary integers each represented within a range of 2n bits.

Multiplication by 5 is executed through the following processing steps P1 to P3.

In processing step P1, the multiplicand X is divided into upper n bits Xl and lower n bits X2, and each is stored in register R1.
, set in register R2. Also.

The multiplier Y is defined as Yl for the upper n bits and Y2 for the lower n bits.
and set them in register R3 and register R4, respectively.

In processing step P2, for the multiplicand X removed from registers R1 and R2, the upper n bits are shifted to the left by 1 bit, and the most significant bit of the lower n bits is transferred to the least significant bit of the upper n bits. Similarly, for the multiplier Y assigned to registers R3 and R4.

The upper n bits are shifted to the left by one bit, and the most significant bit of the lower n bits is carried into the least significant bit of the upper n bits.

Next, in processing step P3, the upper n bits X1 of the multiplicand
Based on the value of the upper n bits Y2 of the multiplier Y, the cases are divided and overflow is detected.If an overflow does not occur, the product of the multiplicand calculate.

[Effect]

In the present invention, by the summer calculator 10 in which one word has n bits, 2n
In performing multiplication of the multiplicand X1 and the multiplier Y expressed within the range of bits, first, each is divided into n bits in processing step P1.

If you execute a multiplication instruction as is between these n bits, the first bit of the lower n bits will be treated as a sign bit, so if this bit happens to be "1'", the calculation of a partially negative number will be performed. You will be killed. Therefore, in processing step P2, the first bit of the lower n bits is
Manipulate to the least significant bit of the upper n bits. The original value of the upper n bits is shifted to the left one bit at a time.

Next, in processing step P3, an overflow check is performed, and the product and sum of each n bit are calculated so that the result of one multiplication is expressed within the range of 2n bits (2n-1 bits as the effective digits of Oga). Calculate and obtain the desired calculation result.

〔Example〕

FIG. 2 is a diagram of an application system according to an embodiment of the present invention, and FIG. 3 is an example of processing according to an embodiment of the present invention. FIG. 4 shows a processing flow of an embodiment of the present invention.

The invention may be implemented in a system such as that shown in FIG. 2, for example. In Figure 2, 20 is the FO that is the result of compiling a program written in the FORTRAN language.
In the RTRAN object program, 21 represents a parameter list, and 22 represents a 63-bit multiplication function routine provided as a library.

Conventionally, a program using FORTRA or N language has 16
Multiplication between 3-bit integer types was not possible, which was a specification restriction. In this embodiment, when performing multiplication of 63-bit integer type, the FORTRAN object program 20 performs the following:
A parameter list 21 consisting of a multiplicand X1, a multiplier Y, and a result area each of 63-bit integer type is created, and a 63-bit multiplication function routine 22 prepared in advance is called.

The 63-bit multiplication function routine 22 executes 63-bit integer type multiplication through the process shown in FIG. Then, the 1 multiplication result is set in the result area of the parameter list 21, and the process returns to the calling FORTRAN object program 20.

For example, in the FORTRAN object program 20 as shown in FIG.

RL-2147483648 car 2” Suppose we want to perform the multiplication of .

FORTRAN object program 20.

A parameter list 21 as shown in FIG.

The 63-bit multiplication routine 22 is shown in FIG. 3(C).

+d), the multiplicand X1 and the multiplier Y are each 3
Divide into 2 bits XI, X2 and Yl, Y2,
．． The first bit of Y2 is XI respectively.

In addition, FIG. 3(C) performs the process of carrying into Yl.

In fdl, numerical values are expressed in hexadecimal digits.

The principle of the calculation is as follows.

Consider z=x−y. Here, X≧0. Let it be Y2O.

X−Xl・2sI→−X2. Y-Yl・2”+Y2(0
≦X2. Y2≦211).

Z−X −Y −XI −YL = 2”+ (XI −Y2+X2−
Yl)X2''+X2・Y2, where Xl・Yl ≧O

In order for Z≦20.

It must be XI-Yl≦2.

The combinations (XI, Yl) that meet this requirement result in the following combinations.

The processing based on this case is as follows.

1) When Xi-0, Yl is 0 This can be done by calculating Z-X2·Y2.

ti) When Xi-Y1=1, Z-2°+(X2+Y2)2''+X2-Y2.

2≦261.

(X2+Y2)2”+X2・Y2≦2thj・・・・・・
・Equivalent to (1).

X2<2", Y2 (from 2".

Since X2+Y2<2'' and X2·Y2<2'', overflow will not occur in the logical addition instruction in the calculation of the left side of equation (1).

Therefore, the fact that formula (l) holds is equivalent to the fact that overflow does not occur in x-y, and the equality sign in formula (l) can only hold if x-y<o. It is.

1n) In the case of (Xi-0 and Yl≠0) or (XI≠0 and Yl-0) Generality is not lost even if it is assumed that X1≠O and Yl-0.

z-x i・Y2・2! I+X2・Y2.

Z≦21.

Xl・Y2・2寥1+X2・Y2≦2°・・・・・・(
It becomes the same value as 2). Therefore, by calculating Xl・Y2.

Unless the upper 4 bytes (32 bits) are 0.

There will be overflow.

1v) (X1=2 and Yl-1) or (X 1-1 and Yl-2) In this case, Xt・Y2+X2・Yl-0 and X2・Y2
From #0, if X2-Y2-0 is 5 and x-y<o, overflow occurs.

v) When Xi≧2 and Y1≧2, there is an overflow of two digits because Xl-Yl-2"≧2thst".

Using the above principles of arithmetic, multiplication of 63-bit integer type and overflow detection are performed using the process shown in Figure 4.
Hereinafter, a description will be given according to the processes Φ to ■ shown in FIG. 4, which are performed as follows.

■ Multiplicand X and multiplier Y are divided into the upper and lower three
Divide into 2 bits each and divide the resulting XI.

Set X2, Yl, and Y2 in registers, respectively.

■ If X is a negative number, reverse the sign to make it a positive number.

This process is performed as follows.

If xi<o, put -XI-1 in Xl.

Furthermore, if X2 is not the minimum value, -X2 is entered into X2. Remember that we reversed the sign of X (.

Similarly, if Y is a negative number, the sign is reversed to make it a positive number.

(2) Next, the first bit of X2 is transferred to XI. This process is performed as follows.

Combine XI and X2 and shift 1 bit to the left.

Shift only X2 to the right by 1 bit.

Similarly, the first bit of Y2 is carried into the least significant bit of Yl.

Processing i to processing V are classified based on the values of Φ Xl and Yl.

■ According to the principle of calculation described above, overflow is detected according to each case, and if no overflow occurs, the product (Z
). Note that if X and Y are negative numbers, the calculation is performed by converting them to positive numbers by reversing the sign, so in the end, if only one of the original X or Y is a negative number,
Reverse the sign of the product Z to represent 2 as a negative number.

〔Effect of the invention〕

As explained above, 1.According to the present invention, 2.For example, 1 word is 3.
It is now possible to perform 63-bit integer type multiplication on a 2-bit computer without using floating-point instructions, improving calculation accuracy in application programs and reducing the processing load.

[Brief explanation of the drawing]

FIG. 1 shows a configuration example of the present invention. FIG. 2 shows an example of a general system according to an embodiment of the present invention. FIG. 3 is an example of processing according to an embodiment of the present invention. FIG. 4 shows a processing flow of an embodiment of the present invention. In the figure, 10 is a computer, and P1 to P3 are processing steps. R1-R4 are registers, X is a multiplicand, and Y is a multiplier.

Claims (1)

[Scope of Claims] Using a computer that is equipped with a plurality of registers that hold n-bit data and has a multiplication instruction execution mechanism for multiplying a multiplicand by an n-bit binary integer and a multiplier by an n-bit binary integer, 2, each represented within 2n bits
A binary integer multiplication processing method for multiplying a multiplicand X and a multiplier Y, which are base integers, by dividing each of the multiplicand X and the multiplier Y into upper n bits and lower n bits, and multiplying each of the n bits Processing process (P1) for allocating to registers: For each of the multiplicand The process of carrying into the least significant bit of n bits (
P2) and the values of the upper n bits of the multiplicand A binary integer multiplication processing method, comprising a processing step (P3) of calculating a product of a multiplicand X and a multiplier Y.