CN111596888A - Method for realizing 32-bit unsigned number integer multiplication on low-bit-width MCU (microprogrammed control Unit) - Google Patents
Method for realizing 32-bit unsigned number integer multiplication on low-bit-width MCU (microprogrammed control Unit) Download PDFInfo
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- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
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- G06F7/523—Multiplying only
Abstract
The invention discloses a method for realizing 32-bit unsigned integer multiplication on a low-bit-width MCU (microprogrammed control Unit), wherein X is A and B. (X, A and B are 32-bit unsigned integer data types) on the MCU platform lower than 32 bits, the direct operation result X of the above formula will overflow directly, and the theoretical operation value satisfying A X B must be less than 2 to use the above multiplication correctly32The method includes the steps of representing 32-bit unsigned integer data A as ①, and 32-bit unsigned integer data B as ②, step S2, substituting ① and ② into A B to obtain ③, representing (AH B + AL BH) in expression ③ as ④, substituting ④ into ③ to obtain ② 0, and representing D in expression ⑤ as DH 216+ DL ⑥, expression ⑥ for DL 216The method has the advantages that the method can be realized on an MCU platform with less than 32 bits, and the method can be used as a basic method and can be expanded to be applied to unsigned number multiplication operation with the width of a plurality of multiple bits (n × 16).
Description
Technical Field
The invention particularly relates to the technical field of 32-bit unsigned number integer multiplication, and particularly relates to a method for realizing 32-bit unsigned number integer multiplication on a low-bit-width MCU.
Background
In some application fields, such as RSSI monitoring report of an optical module, RSSI data operation processing is required to be completed within a very short time, RSSI calibration parameters are usually floating point numbers, but due to the cost and the like, an MCU (microprogrammed control unit) used by the optical module is basically not provided with a hardware floating point operation unit, the floating point operations are realized only by software codes, the software floating point operation consumes time, the operation speed is limited by MCU master frequency, and the RSSI report time requirement is usually not met; to solve this problem, it is a common practice to amplify and then rounding the floating point calibration parameters during RSSI calibration, and write the integer calibration parameters into the MCU. The MCU carries out integer arithmetic processing on the calibration parameters and the sampling ADC value in the working process of the optical module and finishes RSSI report, the processing method utilizes integer arithmetic to replace floating-point arithmetic, not only the function is realized in the acceptable precision loss range, but also the time requirement is met, and the integer arithmetic replaces the floating-point arithmetic and brings a disadvantage: integer arithmetic can handle a much smaller range of data than floating-point arithmetic. For example: for a 1 MCU platform with 16 bits, the compiler supports maximum integer data of 32 bits, and the multiplication result of two 32-bit integer data is 64 bits, and the value of the result has overflowed.
Disclosure of Invention
The invention aims to overcome the problems in the prior art and provides a method for realizing 32-bit unsigned integer multiplication on a low-bit-width MCU;
a method of implementing a 32-bit unsigned integer multiply operation on a low bit wide MCU, wherein X is a. (X, A and B are 32-bit unsigned integer data types) on the MCU platform lower than 32 bits, the direct operation result X of the above formula will overflow directly, and the theoretical operation value satisfying A X B must be less than 2 to use the above multiplication correctly32；
The method comprises the following steps:
step S1: expressing 32-bit unsigned integer data A as a first, and expressing 32-bit unsigned integer data B as a second;
step S2: substituting the first and the second into A and B to obtain a third;
step S3: expressing (AH + BL + AL + BH) in the expression (c) as (d);
step S4: bringing the expression (iv) into (iii) to obtain (v);
step S5: d in the expression fifth is represented as DH 216+ DL to obtain (l);
step S6: in the expression (VI), DL is 216+ AL is BL and is represented as (VII);
step S7: carrying the expression to the sixth step to obtain the eighty percent;
step S7: storing the operation result in the expression (b) as the upper 32 bits of 64 bits;
step S8: calculating a temperature compensation amount in RSSI monitoring;
in the step S1, in the above step,32-bit unsigned integer data a is denoted as a ═ AH × 216+ AL, where AH is the upper 16 position, AL is the lower 16 position, and B is represented by B ═ BH × 216+ BL, example: 0x12345678 ═ 0x1234 x 216+0x5678, 0x1234 is AH, 0x5678 is AL.
In step S2, a ═ AH × 2 is added16+ AL and B ═ BH 216Substituting A with B into BL to obtain A with B (AH with BH) 232+(AH*BL+AL*BH)*216+AL*BL。
In step S3, the expression AH × BL + AL × BH is expressed as AH × BL + AL × BH ═ C × 232The expression AH + AL BH ═ C ═ 2 is expressed by the mode + D32+ D ═ AH × BL + AL × BH; if D is<AH × BL is true, then C ═ 1, else C ═ 0.
In step S4, the expression AH × BL + AL × BH ═ C × 232+ D is substituted by a × B ═ AH × BH) × 232+(AH*BL+AL*BH)*216+ AL × BL yields: AH + BL + AL BH ═ C ═ 232+ D into A + B ═ (AH + BH) × 232+(AH*BL+ AL*BH)*216+ AL + BL yields A + B ═ (AH + BH + C + 2)16)*232+D*216+ AL*BL。
In the step S5, the expression a ═ B ═ (AH ═ BH + C ═ 216)*232+D*216D in + AL + BL is represented by DH + 216+ DL is obtained: a × B ═ (AH × BH + C × 2)16+ DH)*232+DL*216+AL*BL，
In step S6, expression a ═ B ═ (AH × BH + C ═ 216+DH)*232+ DL*216+ AL + BL DL 216+ AL + BL is denoted as DL 216+AL*BL＝E*232+ F, expression DL 216+AL*BL＝E*232+ F ═ DL 216+ AL × BL; if F<DL*216If yes, E ═ 1, otherwise E ═ 0, the expression DL ═ 216+ AL*BL＝E*232+ F into A + B ═ (AH + BH + C + 2)16+DH)*232+DL*216+ AL × BL yields: a × B ═ (AH × BH + C × 2)16+DH+E)*232+F。
In step S7, expression a ═ B ═ (AH × BH + C ═ 216+DH+E)*232+ F AH + C216The result of the operation of + DH + E is stored as the upper 32 bits of 64 bits, and F is stored as the lower 32 bits of 64 bitsAnd (5) storing. Thus, two 32-bit unsigned number multiplication operations and result storage are realized.
In step S8, X ═ ADC × K × Δ T/224In the above formula, K is an amplified temperature compensation slope integer, and is assumed to be 0x107FE at most; 13 bit ADC maximum value 0x1 FFF; Δ T is a temperature difference maximum of 0x 64; 224Is the slope magnification; to reduce the loss of accuracy, not only the temperature compensation slope is performed by 224At magnification, 224 is also needed to be placed at the end of the integer division. From the above formula, it can be seen that the maximum value of ADC K Δ T is 0xCF0AE7750, and the operation result value is 36 bits, which cannot be realized on the low-bit-width MCU by directly using the multiplication formula. We can first make ADC1 ═ ADC × T (the value of ADC1 less than 232 can be directly implemented by multiplication); then, the method described in the present invention is used to solve ADC2 ═ ADC1 × K to obtain ADC2 with a high 32-bit value of 0x0c and a low 32-bit value of 0xF0AE 7750; finally X-ADC 2/224 (0X 0000000C)<<(32-24))+(0xCF0AE7750>>24)＝0xCF0。
The benefit effects of the invention are:
a multiplication method of two 32-bit unsigned integer numbers; the method has the advantages that the method can be realized on an MCU platform with less than 32 bits; the method is used as a basic method and can be extended to be applied to multiple multi-bit (n × 16) wide unsigned number multiplication.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention relates to a method for realizing 32-bit unsigned number integer multiplication on a low-bit-width MCU, which is characterized in that X is A and B. (X, A and B are 32-bit unsigned integer data types) on the MCU platform lower than 32 bits, the direct operation result X of the above formula will overflow directly, and the theoretical operation value satisfying A X B must be less than 2 to use the above multiplication correctly32；
The method comprises the following steps:
step S1: expressing 32-bit unsigned integer data A as a first, and expressing 32-bit unsigned integer data B as a second;
step S2: substituting the first and the second into A and B to obtain a third;
step S3: expressing (AH + BL + AL + BH) in the expression (c) as (d);
step S4: bringing the expression (iv) into (iii) to obtain (v);
step S5, D in expression ⑤ is represented as DH 216+ DL to ⑥;
step S6 expression ⑥ for DL 216+ AL × BL is denoted ⑦;
step S7: carrying the expression to the sixth step to obtain the eighty percent;
step S7: storing the operation result in the expression (b) as the upper 32 bits of 64 bits;
step S8: calculating a temperature compensation amount in RSSI monitoring;
in step S1, the 32-bit unsigned integer data a is expressed as a ═ AH × 216+ AL, where AH is the upper 16 position, AL is the lower 16 position, and B is represented by B ═ BH × 216+ BL, example: 0x12345678 ═ 0x1234 x 216+0x5678, 0x1234 is AH, 0x5678 is AL.
In step S2, a ═ AH × 216+ AL and B ═ BH 216Substituting A with B into BL to obtain A with B (AH with BH) 232+(AH*BL+AL*BH)*216+AL*BL。
In step S3, the expression AH × BL + AL × BH is expressed as AH × BL + AL × BH ═ C × 232The expression AH + AL BH ═ C ═ 2 is expressed by the mode + D32+ D ═ AH × BL + AL × BH; if D is<AH × BL is true, then C ═ 1, else C ═ 0.
In step S4, the expression AH × BL + AL × BH ═ C × 2 is expressed32+ D into A + B ═ (AH + BH) × 232+(AH*BL+AL*BH)*216+ AL × BL yields: AH + BL + AL BH ═ C ═ 232+ D into A + B ═ (AH + BH) × 232+(AH*BL+AL* BH)*216+ AL + BL yields A + B ═ (AH + BH + C + 2)16)*232+D*216+AL* BL。
In step S5, expression a × B ═ B(AH*BH+C*216)*232+D*216D in + AL + BL is represented by DH + 216+ DL is obtained: a × B ═ (AH × BH + C × 2)16+DH)*232+DL*216+AL*BL，
In step S6, expression a ═ B ═ (AH × BH + C ═ 216+DH)*232+DL*216The + AL + BL in DL 216+ AL + BL is expressed as DL 216+AL*BL＝E*232+ F, expression DL 216+ AL BL ═ E ═ 232+ F ═ DL 216+ AL × BL; if F<DL 216 is true, E is 1, else E is 0, and the expression DL 2 is used16+ AL × BL ═ E × 232+ F to a × B ═ AH × BH + C × 216+DH)*232+DL*216+ AL × BL yields: a × B ═ (AH × BH + C × 2)16+DH+E)*232+F。
In step S7, expression a ═ B ═ (AH × BH + C ═ 216+DH+E)*232+ F AH + C216The operation result of + DH + E is stored as the upper 32 bits of 64 bits, and F is stored as the lower 32 bits of 64 bits. Thus, two 32-bit unsigned number multiplication operations and result storage are realized.
In step S8, K in the formula X ═ ADC × K × Δ T/224 is an amplified temperature compensation slope rounded value, and is assumed to be 0X107FE at maximum; 13 bit ADC maximum value 0x1 FFF; Δ T is a temperature difference maximum of 0x 64; 224Is the slope magnification; to reduce the loss of accuracy, not only the temperature compensation slope is performed by 224Magnification, and 2 is also required24Put to the end and carry on the integer division. From the above formula, it can be seen that the maximum value of ADC K Δ T is 0xCF0AE7750, and the operation result value is 36 bits, which cannot be realized on the low-bit-width MCU by directly using the multiplication formula. We can first make ADC1 ═ ADC × T (value of ADC1 is less than 2)32Can be directly realized by multiplication); then, the method described in the present invention is used to solve ADC2 ═ ADC1 × K to obtain ADC2 with a high 32-bit value of 0x0c and a low 32-bit value of 0xF0AE 7750; last X ═ ADC2/224＝(0x0000000C<<(32-24))+(0xCF0AE7750>>24)＝0xCF0。
One specific application of this embodiment is: calculating the temperature compensation amount in the RSSI monitoring: x is ADC K Δ T/224In the above formula, K is an amplified temperature compensation slope integer, and is assumed to be 0x107FE at most;13 bit ADC maximum value 0x1 FFF; Δ T is a temperature difference maximum of 0x 64; 224Is the slope magnification; to reduce the loss of accuracy, not only the temperature compensation slope is performed by 224Magnification, and 2 is also required24Put to the end and carry on the integer division. The maximum value of ADC (analog to digital converter) K delta T is 0xCF0AE7750, the operation result value is 36 bits, and the operation cannot be realized on the MCU with low bit width by directly utilizing a multiplication formula. We can first make ADC1 ═ ADC × T (value of ADC1 is less than 2)32Can be directly realized by multiplication); then, the method described in the present invention is used to solve ADC2 ═ ADC1 × K to obtain ADC2 with a high 32-bit value of 0x0c and a low 32-bit value of 0xF0AE 7750; last X ═ ADC2/224＝(0x0000000C<<(32-24))+ (0xCF0AE7750>>24)＝0xCF0。
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or the like described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The preferred embodiments of the invention disclosed above are intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (9)
1. A method of implementing a 32-bit unsigned integer multiply operation on a low bit wide MCU, wherein X is a. (the data types of X, A and B are both 32-bit unsigned integers) on MCU platforms below 32 bits,the direct operation result X of the above formula will overflow directly, and the theoretical operation value satisfying A X B must be less than 2 to use the above multiplication correctly32；
The method comprises the following steps:
step S1: expressing 32-bit unsigned integer data A as a first, and expressing 32-bit unsigned integer data B as a second;
step S2: substituting the first and the second into A and B to obtain a third;
step S3: expressing (AH + BL + AL + BH) in the expression (c) as (d);
step S4: bringing the expression (iv) into (iii) to obtain (v);
step S5, D in expression ⑤ is represented as DH 216+ DL to ⑥;
step S6 expression ⑥ for DL 216+ AL × BL is denoted ⑦;
step S7: carrying the expression to the sixth step to obtain the eighty percent;
step S7: storing the operation result in the expression (b) as the upper 32 bits of 64 bits;
step S8: the temperature compensation amount is calculated in the RSSI monitoring.
2. A method of implementing a 32-bit unsigned integer multiply operation on a low bit width MCU according to claim 1, characterized by: in step S1, the 32-bit unsigned integer data a is expressed as a ═ AH × 216+ AL, where AH is the upper 16 position, AL is the lower 16 position, and B is represented by B ═ BH × 216+ BL, example: 0x12345678 ═ 0x1234 x 216+0x5678, 0x1234 is AH, 0x5678 is AL.
3. A method of implementing a 32-bit unsigned integer multiply operation on a low bit width MCU according to claim 1, characterized by: in step S2, a ═ AH × 2 is added16+ AL and B ═ BH 216Substituting A with B into BL to obtain A with B (AH with BH) 232+(AH*BL+AL*BH)*216+AL*BL。
4. An implementation of 32-bit unsigned integer on a low bit width MCU according to claim 1A method of type multiplication, characterized by: in step S3, the expression AH × BL + AL × BH is expressed as AH × BL + AL × BH ═ C × 232The expression AH + AL BH ═ C ═ 2 is expressed by the mode + D32+ D ═ AH × BL + AL × BH; if D is<AH × BL is true, then C ═ 1, else C ═ 0.
5. A method of implementing a 32-bit unsigned integer multiply operation on a low bit width MCU according to claim 1, characterized by: in step S4, the expression AH × BL + AL × BH ═ C × 2 is used32+ D into A + B ═ (AH + BH) × 232+(AH*BL+AL*BH)*216+ AL × BL yields: AH + BL + AL BH ═ C ═ 232+ D into A + B ═ (AH + BH) × 232+(AH*BL+AL*BH)*216+ AL + BL yields A + B ═ (AH + BH + C + 2)16)*232+D*216+AL*BL。
6. A method of implementing a 32-bit unsigned integer multiply operation on a low bit width MCU according to claim 1, characterized by: in the step S5, the expression a ═ B ═ (AH ═ BH + C ═ 216)*232+D*216D in + AL + BL is represented by DH + 216+ DL is obtained: a × B ═ (AH × BH + C × 2)16+DH)*232+DL*216+AL*BL。
7. A method of implementing a 32-bit unsigned integer multiply operation on a low bit width MCU according to claim 1, characterized by: in step S6, expression a ═ B ═ (AH × BH + C ═ 216+DH)*232+DL*216+ AL + BL DL 216+ AL + BL is denoted as DL 216+AL*BL＝E*232+ F, expression DL 216+AL*BL＝E*232+ F ═ DL 216+ AL × BL; if F<DL*216If yes, E ═ 1, otherwise E ═ 0, the expression DL ═ 216+AL*BL＝E*232+ F into A + B ═ (AH + BH + C + 2)16+DH)*232+DL*216+ AL × BL yields: a × B ═ (AH × BH + C × 2)16+DH+E)*232+F。
8. According to the claims1, the method for implementing 32-bit unsigned integer multiplication on a low-bit-width MCU is characterized in that: in step S7, expression a ═ B ═ (AH × BH + C ═ 216+DH+E)*232+ F AH + C216The operation result of + DH + E is stored as the upper 32 bits of 64 bits, and F is stored as the lower 32 bits of 64 bits. Thus, two 32-bit unsigned number multiplication operations and result storage are realized.
9. A method of implementing a 32-bit unsigned integer multiply operation on a low bit width MCU according to claim 1, characterized by: in step S8, X ═ ADC × K × Δ T/224In the above formula, K is an amplified temperature compensation slope integer, and is assumed to be 0x107FE at most; 13 bit ADC maximum value 0x1 FFF; Δ T is a temperature difference maximum of 0x 64; 224Is the slope magnification; to reduce the loss of accuracy, not only the temperature compensation slope is performed by 224Magnification, and 2 is also required24Put to the end and carry on the integer division. From the above formula, it can be seen that the maximum value of ADC K Δ T is 0xCF0AE7750, and the operation result value is 36 bits, which cannot be realized on the low-bit-width MCU by directly using the multiplication formula. We can first make ADC1 ═ ADC × T (value of ADC1 is less than 2)32Can be directly realized by multiplication); then, the method described in the present invention is used to solve ADC2 ═ ADC1 × K to obtain ADC2 with a high 32-bit value of 0x0c and a low 32-bit value of 0xF0AE 7750; last X ═ ADC2/224＝(0x0000000C<<(32-24))+(0xCF0AE7750>>24)＝0xCF0。
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Application publication date: 20200828 |