CN109687870B - Charge redistribution type SARADC capacitance mismatch correction method and system - Google Patents
Charge redistribution type SARADC capacitance mismatch correction method and system Download PDFInfo
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- CN109687870B CN109687870B CN201811617907.7A CN201811617907A CN109687870B CN 109687870 B CN109687870 B CN 109687870B CN 201811617907 A CN201811617907 A CN 201811617907A CN 109687870 B CN109687870 B CN 109687870B
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Abstract
The application discloses a charge redistribution type SARADC capacitance mismatch correction method, which comprises the steps of calculating SARADC straightFlow mismatch DC err The method comprises the steps of carrying out a first treatment on the surface of the DC-based err Calculating correction coefficients of other capacitances except the 1 st capacitance; and storing a correction coefficient, and calling the correction coefficient to correct the SARADC output when the SARADC works normally. Corresponding systems are also disclosed. The application abandons the traditional background correction, measures and quantizes all the capacitors needing to be corrected before the normal quantization of the circuit, then extracts the required correction coefficient and stores the correction coefficient, adds the correction coefficient to the quantized output code in the digital domain during the normal conversion of the circuit, and does not need to do any processing in the analog domain, thereby achieving the purpose of reducing or eliminating the mismatch of the capacitors, and being applicable to SARADC small-area, low-delay and high-speed index requirements.
Description
Technical Field
The application relates to a charge redistribution type SARADC capacitance mismatch correction method and system, and belongs to the field of semiconductor integrated circuit design.
Background
The successive approximation analog-to-digital converter (SARADC) has higher precision, small power consumption and small area, and with the continuous development of the nano-scale Complementary Metal Oxide Semiconductor (CMOS) process, the high-speed high-precision SARADC has become more and more widely applied in various aspects.
A digital-to-analog converter (DAC) in conventional charge redistribution type SARADC is composed of a capacitor array, and mismatch between unit capacitors becomes an important factor limiting SARADC accuracy due to process variations. The proportional accuracy of the capacitor is positively correlated with the area of the capacitor, and a larger area is required to achieve higher proportional accuracy. Correcting the capacitance mismatch can eliminate or reduce the mismatch error and improve the accuracy of SARADC.
At present, under the nanoscale process, the mainstream correction technology is background correction, and for background correction, the change of device parameters needs to be tracked in real time, so that a complex digital circuit is required, a large amount of chip area and data delay are consumed, and the operation speed of a calibration algorithm is low, so that the background correction algorithm is not applicable to designs with strict requirements on area, delay and speed.
In summary, background correction commonly used at present is not applicable to the index requirements of small area, low delay and high speed of SARADC.
Disclosure of Invention
The application provides a charge redistribution type SARADC capacitor mismatch correction method and system, which solve the problem that the traditional method is not applicable to SARADC small-area, low-delay and high-speed index requirements.
In order to solve the technical problems, the application adopts the following technical scheme:
a charge redistribution type SARADC capacitance mismatch correction method comprises the following steps,
calculating SARADC DC mismatch err ；
DC-based err Calculating correction coefficients of other capacitances except the 1 st capacitance;
and storing a correction coefficient, and calling the correction coefficient to correct the SARADC output when the SARADC works normally.
Calculating DC err The process comprises shorting differential input terminals of SARADC, measuring obtained SAR ADC output DC out Is DC err 。
The process of calculating the nth capacitance correction coefficient is,
control of the nth capacitor C n Sampling reference high level Reft, controlling other capacitors to sample reference low level Refb, and controlling the capacitor C greater than or equal to the nth bit n The output is 0;
the n-th capacitance correction coefficient is,
wherein Ke n Ke is the nth capacitance correction coefficient i For the i-th capacitance correction coefficient, i E [2, n-1 ]]，S n T for SARADC current actual output n For SARADC current theoretical output, D i And outputting a result for the binary bit corresponding to the ith bit capacitor.
The output correction process is that if the binary bit output result corresponding to a certain capacitor is 1, the SARADC output is added with the capacitance correction coefficient; if the binary bit output result corresponding to a certain capacitor is 0, no processing is needed in the SARADC output.
A charge redistribution type SARADC capacitance mismatch correction system, comprising,
and the direct current mismatch calculation module is used for: calculating SARADC DC mismatch err ；
Correction coefficient calculation module: DC-based err Calculating correction coefficients of other capacitances except the 1 st capacitance;
and a correction module: and storing a correction coefficient, and calling the correction coefficient to correct the SARADC output when the SARADC works normally.
Calculating DC in DC mismatch calculation module err The process comprises shorting differential input terminals of SARADC, measuring obtained SAR ADC output DC out Is DC err 。
The process of calculating the nth capacitance correction coefficient by the correction coefficient calculating module is that,
control of the nth capacitor C n Sampling reference high level Reft, controlling other capacitors to sample reference low level Refb, and controlling the capacitor C greater than or equal to the nth bit n The output is 0;
the n-th capacitance correction coefficient is,
wherein Ke n Ke is the nth capacitance correction coefficient i For the i-th capacitance correction coefficient, i E [2, n-1 ]]，S n T for SARADC current actual output n For SARADC current theoretical output, D i And outputting a result for the binary bit corresponding to the ith bit capacitor.
The output correction process in the correction module is that if the binary bit output result corresponding to a certain capacitor is 1, the SARADC output is added with the capacitance correction coefficient; if the binary bit output result corresponding to a certain capacitor is 0, no processing is needed in the SARADC output.
A computer readable storage medium storing one or more programs, characterized by: the one or more programs include instructions, which when executed by a computing device, cause the computing device to perform a charge redistribution type SARADC capacitance mismatch correction method.
A computing device comprising one or more processors, memory, and one or more programs, wherein one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs comprising instructions for performing a charge redistribution type sar adc capacitance mismatch correction method.
The application has the beneficial effects that: the application abandons the traditional background correction, measures and quantizes all the capacitors needing to be corrected before the normal quantization of the circuit, then extracts the required correction coefficient and stores the correction coefficient, adds the correction coefficient to the quantized output code in the digital domain during the normal conversion of the circuit, and does not need to do any processing in the analog domain, thereby achieving the purpose of reducing or eliminating the mismatch of the capacitors, and being applicable to SARADC small-area, low-delay and high-speed index requirements.
Drawings
FIG. 1 is a flow chart of the present application;
FIG. 2 is a diagram of SARADC segmented DAC capacitive array and timing diagram;
FIG. 3 is a graph of the DNL error simulation results of the pre-uncorrected SARADC;
FIG. 4 is a graph of INL error simulation results of SARADC before uncorrected;
FIG. 5 is a diagram of the DNL error simulation results of the corrected SARADC;
FIG. 6 is a graph showing the results of INL error simulation of corrected SARADC.
Detailed Description
The application is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present application, and are not intended to limit the scope of the present application.
The SARADC has two working modes, one is a correction mode, the other is a normal working mode, correction coefficients of other capacitors except the 1 st capacitor are obtained in the correction mode, the 1 st capacitor does not need correction, so that the correction coefficients are not needed, the specific correction sequence is that the correction coefficients of the first 1 bit are needed from the lower position to the higher position, the correction process needs to know the binary bit output result corresponding to the current capacitor, and whether the first 1 bit correction coefficient acts to calculate the correction coefficient of the current capacitor is determined according to the binary bit output result; in a normal working mode, determining whether a correction coefficient is effective according to a binary bit output result corresponding to each capacitor, and if the binary bit output result corresponding to a certain capacitor is 1, adding the capacitance correction coefficient to the output of SARADC; if the binary bit output result corresponding to a certain capacitor is 0, the SARADC output is not required to be processed and is normally output.
The specific process of the charge redistribution type SARADC capacitance mismatch correction method is shown in fig. 2:
step 1, calculating the direct current mismatch DC of SARADC err 。
Calculating DC err The process of (1) is as follows: shorting differential input ends of SARADC, and measuring obtained SAR ADC output DC out Is DC err 。
Step 2, DC-based err And calculating correction coefficients of other capacitances except the 1 st capacitance.
The process of calculating the nth capacitance correction coefficient is as follows:
21 As shown in FIG. 3, the sampling phase controls the nth bit capacitance C n Sampling reference high level Reft, controlling other capacitors to sample reference low level Refb, and controlling quantization phase to be greater than or equal to nth bit capacitor C n The output is 0.
22 The n-th capacitance correction coefficient is:
wherein Ke n Ke is the nth capacitance correction coefficient i For the i-th capacitance correction coefficient, i E [2, n-1 ]]，S n T for SARADC current actual output n For SARADC current theoretical output, D i And outputting a result for the binary bit corresponding to the ith bit capacitor.
And step 3, storing a correction coefficient, calling the correction coefficient when the SARADC works normally, and correcting the SARADC output.
The output correction process is as follows: if the binary bit output result corresponding to a certain capacitor is 1, adding the capacitance correction coefficient to the SARADC output; if the binary bit output result corresponding to a certain capacitor is 0, no processing is needed in the SARADC output.
For example, an 8-bit SARADC, assuming that the output result is 10101010 (binary bit representation), the corrected output is 10101010+Ke 8 +Ke 6 +Ke 4 +Ke 2 -DC err 。
To verify the effect described above, MATLAB simulations of Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) were performed, with specific results shown in FIGS. 3-6. The maximum of the differential nonlinearity of SARADC before correction is-8 LSB, the maximum of the integral nonlinearity is 4.3LSB, and uncorrected SARADC has error codes in the conversion process; the maximum value of the corrected SARADC differential nonlinearity is +/-0.5 LSB, and the maximum value of the integral nonlinearity is 0.6LSB. The front and back simulation results are synthesized, and the SARADC performance is effectively improved by the correction method.
The method abandons the traditional background correction, measures and quantizes all the capacitors to be corrected before the circuit is quantized normally, then extracts and stores the required correction coefficients, adds the correction coefficients to the quantized output codes in the digital domain during the normal conversion of the circuit, and does not need to do any processing in the analog domain, thereby achieving the purpose of reducing or eliminating the mismatch of the capacitors, and being applicable to SARADC small-area, low-delay and high-speed index requirements.
A charge redistribution type SARADC capacitance mismatch correction system comprising:
and the direct current mismatch calculation module is used for: calculating SARADC DC mismatch err . Calculating DC in DC mismatch calculation module err The process of (1) is as follows: shorting differential input ends of SARADC, and measuring obtained SAR ADC output DC out Is DC err 。
Correction coefficient calculation module: DC-based err And calculating correction coefficients of other capacitances except the 1 st capacitance.
The process of calculating the nth capacitance correction coefficient by the correction coefficient calculating module is as follows:
control of the nth capacitor C n Sampling reference high level Reft, controlling other capacitors to sample reference low level Refb, and controlling largeAt or equal to the nth capacitor C n The output is 0;
the n-th capacitance correction coefficient is,
wherein Ke n Ke is the nth capacitance correction coefficient i For the i-th capacitance correction coefficient, i E [2, n-1 ]]，S n T for SARADC current actual output n For SARADC current theoretical output, D i And outputting a result for the binary bit corresponding to the ith bit capacitor.
And a correction module: and storing a correction coefficient, and calling the correction coefficient to correct the SARADC output when the SARADC works normally.
The output correction process in the correction module is as follows: if the binary bit output result corresponding to a certain capacitor is 1, adding the capacitance correction coefficient to the SARADC output; if the binary bit output result corresponding to a certain capacitor is 0, no processing is needed in the SARADC output.
A computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computing device, cause the computing device to perform a charge redistribution type sar adc capacitance mismatch correction method.
A computing device comprising one or more processors, memory, and one or more programs, wherein one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs comprising instructions for performing a charge redistribution type sar adc capacitance mismatch correction method.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing is illustrative of the present application and is not to be construed as limiting thereof, but rather as providing for the use of additional embodiments and advantages of all such modifications, equivalents, improvements and similar to the present application are intended to be included within the scope of the present application as defined by the appended claims.
Claims (8)
1. The charge redistribution type SARADC capacitance mismatch correction method is characterized in that: comprises the steps of,
calculating SARADC DC mismatch err ；
DC-based err Calculating correction coefficients of other capacitances except the 1 st capacitance; the specific process for calculating the nth capacitance correction coefficient is as follows:
control of the nth capacitor C n Sampling reference high level Reft, controlling other capacitors to sample reference low level Refb, and controlling the capacitor C greater than or equal to the nth bit n The output is 0;
the n-th capacitance correction coefficient is,
wherein Ke n Ke is the nth capacitance correction coefficient i For the i-th capacitance correction coefficient, i E [2, n-1 ]]，S n T for SARADC current actual output n For SARADC current theoretical output, D i Outputting a result for the binary bit corresponding to the ith bit capacitor;
and storing a correction coefficient, and calling the correction coefficient to correct the SARADC output when the SARADC works normally.
2. The charge redistribution type SARADC capacitance mismatch correction method according to claim 1, wherein: calculating DC err The process comprises shorting differential input terminals of SARADC, measuring obtained SAR ADC output DC out Is DC err 。
3. The charge redistribution type SARADC capacitance mismatch correction method according to claim 1, wherein: the output correction process is that if the binary bit output result corresponding to a certain capacitor is 1, the SARADC output is added with the correction coefficient of the binary bit corresponding capacitor with the output result of 1; if the binary bit output result corresponding to a certain capacitor is 0, no processing is needed in the SARADC output.
4. The charge redistribution type SARADC capacitance mismatch correction system is characterized in that: comprising the steps of (a) a step of,
and the direct current mismatch calculation module is used for: calculating SARADC DC mismatch err ；
Correction coefficient calculation module: DC-based err Calculating correction coefficients of other capacitances except the 1 st capacitance;
the process of calculating the nth capacitance correction coefficient by the correction coefficient calculating module is as follows:
control of the nth capacitor C n Sampling reference high level Reft, controlling other capacitors to sample reference low level Refb, and controlling the capacitor C greater than or equal to the nth bit n The output is 0;
the n-th capacitance correction coefficient is,
wherein Ke n Ke is the nth capacitance correction coefficient i For the i-th capacitance correction coefficient, i E [2, n-1 ]]，S n T for SARADC current actual output n For SARADC current theoretical output, D i Outputting a result for the binary bit corresponding to the ith bit capacitor;
and a correction module: and storing a correction coefficient, and calling the correction coefficient to correct the SARADC output when the SARADC works normally.
5. The charge redistribution type SARADC capacitance mismatch correction system according to claim 4, wherein: calculating DC in DC mismatch calculation module err The process comprises shorting differential input terminals of SARADC, measuring obtained SAR ADC output DC out Is DC err 。
6. The charge redistribution type SARADC capacitance mismatch correction system according to claim 4, wherein: the output correction process in the correction module is that if the binary bit output result corresponding to a certain capacitor is 1, the SARADC output is added with the correction coefficient of the binary bit corresponding capacitor with the output result of 1; if the binary bit output result corresponding to a certain capacitor is 0, no processing is needed in the SARADC output.
7. A computer readable storage medium storing one or more programs, characterized by: the one or more programs include instructions, which when executed by a computing device, cause the computing device to perform any of the methods of claims 1-3.
8. A computing device, characterized by: comprising the steps of (a) a step of,
one or more processors, memory, and one or more programs, wherein one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs comprising instructions for performing any of the methods of claims 1-3.
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| JP2008118473A (en) * | 2006-11-06 | 2008-05-22 | Sharp Corp | Digital circuit and analog/digital conversion circuit provided with the same |
| CN104113335A (en) * | 2014-01-22 | 2014-10-22 | 西安电子科技大学 | 14-bit high-speed assembly line type analog-to-digital converter |
| CN104242935A (en) * | 2014-09-15 | 2014-12-24 | 电子科技大学 | SAR ADC segmented capacitor mismatch correction method |
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| US8441378B2 (en) * | 2011-08-11 | 2013-05-14 | Pixart Imaging, Inc. | Capacitor mismatch error correction in pipeline analog-to-digital converters |
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| JP2008118473A (en) * | 2006-11-06 | 2008-05-22 | Sharp Corp | Digital circuit and analog/digital conversion circuit provided with the same |
| CN104113335A (en) * | 2014-01-22 | 2014-10-22 | 西安电子科技大学 | 14-bit high-speed assembly line type analog-to-digital converter |
| CN104242935A (en) * | 2014-09-15 | 2014-12-24 | 电子科技大学 | SAR ADC segmented capacitor mismatch correction method |
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