JPH0695848A - Adder and microprocessor using this adder - Google Patents

Abstract

PURPOSE:To execute addition at a high speed, and also, to make a circuit scale small. CONSTITUTION:In the adder for adding an augend of the a value a2 in which two upper bits are equal to each other, and addend of a value b2 in which two upper bits are equal to each other, when carry from the place being lower by one from two upper bits is denoted as c2, when one piece or three pieces of the values a2, b2 and c2 are a value '1' by inverters 20-22, AND gates 30-33 and an OR gate 40, the value '1' is outputted as the lower side bit of two upper bits of a result of addition. In other case, a value '0' is outputted as the lower side bit and when values (a) and (b) are both the value '1', or the value (a) or the value (b) is '1', and also, the value (c) is '0' by AND gates 34, 37 and 38, and an OR gate 41, the value '1' is outputted as the side bit of two upper bits, and in other case, the value '1' is outputted as the upper side bit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adder for adding an augend whose upper two bits are equal to each other and an addend whose upper two bits are equal to each other, and a microprocessor using the adder.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional 4-bit binary adder. This adder includes 1-bit full adders 10 to 13 having the same configuration. 1-bit full adder 1i
(I = 0 to 3) is added to the i-th bit ai of the augend, the i-th bit bi of the addend, and the carry ci from the next lower place,
It outputs the i-th bit si of the sum and ci + 1 to the next higher place.

As shown in FIG. 4, the 1-bit full adder 1i includes inverters 20 to 22 and AND gates 30 to 36.
And OR gates 40 and 41. Sum i
The bit si becomes the value 1 when one or three of the i-th bit ai of the augend, the i-th bit bi of the addend, and the carry ci from the next lower place have the value 1, and become one higher. For carry ci + 1 to the rank, two or more of ai, bi and ci have a value of 1
When, the value becomes 1.

When sign extension is performed to the next highest digit, such as addition of two's complement numbers, the upper two bits of each of the augend and the addend are mutually different. It becomes equal value.

[0005]

However, in the prior art, two 1-bit full adders have been used even for such addition of the upper 2 bits, so that the most significant bit of the sum is from the next lower position. Cannot be obtained until the carry is confirmed, and therefore the addition speed becomes slower, the circuit becomes redundant, the circuit scale becomes large, and the power consumption becomes high.

In view of such problems, an object of the present invention is to provide an adder capable of increasing the addition speed and reducing the circuit scale, and a microprocessor using the adder.

[0007]

According to the present invention, in the adder for adding the augend of the value a whose upper 2 bits are equal to each other and the addend of the value b whose upper 2 bits are equal to each other, When the carry from one place below the upper 2 bits is c, and when 1 or 3 of a, b and c have the value 1, the value 1 is set as the lower side bit of the upper 2 bits of the addition result. A lower bit calculator that outputs the value 0 as the lower bit in other cases, and a and b both have the value 1, or a value 1 when the value of a or b is 1 and the value of c is 0 Is output as the high-order side bits of the high-order 2 bits of the addition result, and a value 0 is output as the high-order side bits at other times.

In the present invention, the addition of the higher-order 2 bits is performed by the higher-order bit calculation unit and the lower-order bit calculation unit, and the configuration thereof is about the same circuit scale as the 1-bit full adder of FIG. Therefore, the circuit scale is about half that of the conventional one. Furthermore, since it is not necessary to wait for the carry of the upper 2 bits from the lower side to the upper side to be confirmed, the addition speed is about 2
Doubled.

In the first aspect of the present invention, for example, as shown in FIG. 1, the lower bit calculating unit inverts the value a2 to obtain the value * a.
The first inverter 20 that outputs 2, the second inverter 21 that inverts the value b2 and outputs the value * b2, the third inverter 22 that inverts the value c2 and outputs the value * c2, and the value a
A first AND gate 30 which outputs a logical product of 2 and a value b2 and a value c2, a second AND gate 31 which outputs a logical product of a value * a2 and a value * b2 and a value c2, and a value * a2 and a value Third AND gate 32 that outputs the logical product of b2 and the value * c2
And a fourth AND gate 33 that outputs a logical product of the value a2, the value * b2, and the value * c2, and the first to fourth AND gates 30.
First OR gate 40 that outputs the logical sum of each output
It has and. In addition, the higher-order bit calculation unit uses the value a2
And AND gate 34 for outputting a logical product of the value b2
A sixth AND gate 37 which outputs a logical product of the value b2 and the value * c2, a seventh AND gate 38 which outputs a logical product of the value a2 and the value * c2, and the fifth to seventh AND gates And a second OR gate 41 for outputting the logical sum of the respective outputs of

In the microprocessor of the present invention, the adder is used as an adder in the arithmetic logic unit (ALU).

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows a 4-bit adder having the same function as in FIG. This adder includes 1-bit full adders 10 and 11 having the same configuration as in FIG. 3 and 1-bit full adder 1 in FIG.
Equivalent 2-bit adder 14 having the same function as 2 and 13
It has and. In the present embodiment, the higher 2 bits of each of the augend and the addend are equal, that is, a3 = a.
2, b3 = b2. Therefore, in FIG. 2, the same value 2 of the third bit a3 of the augend and the third bit b3 of the addend
The input to the bit adder 14 is omitted.

The second bit s2 of the sum is a2 + b2 + c2
Is the lower bit of the augend, the second bit a2 of the augend, the second bit b2 of the addend, and one or three of the carry c2 from the 1-bit full adder 11 have the value 1, In other cases, the value is 0. That is, the logical product is ..., the logical sum is ∪,
When the inversion is represented by *, s2 = (a2 · b2 · c2) ∪ (* a2 · * b2 · c
2) ∪ (* a2 ・ b2 ・ * c2) ∪ (a2 ・ * b2 ・ *
c2).

Therefore, the equivalent 2-bit adder 14 has an inverter 20 that inverts a2 and outputs * a2, and an inverter 2 that inverts b2 and outputs * b2, as shown in FIG.
1 and an inverter 22 that inverts c2 and outputs * c2
AND gate 30 that outputs the logical product of a2, b2, and c2, AND gate 31 that outputs the logical product of * a2, * b2, and c2, and the logical product of * a2, b2, and * c2. AND gate 32 for outputting, a2, * b2, and * c2
AND gate 33 that outputs the logical product of AND and OR gate 4 that outputs the logical sum of the outputs of AND gates 30 to 33.
0 and the output of the OR gate 40 is the second bit s of the sum.
2

The upper bits of a2 + b2 + c2 are as follows: c3 = (a2 · b2) ∪ (b2 · c2) ∪ (b2 · a
2) The third bit s3 of the sum is the lower bit of a2 + b2 + c3, and if the logical expression is simplified, s3 = (a2 · b2) ∪ (b2 · * c2) ∪ (* c2 ·
a2).

Therefore, in FIG. 1, the equivalent 2-bit adder 14 has an AND gate 34 which outputs a logical product of a2 and b2, an AND gate 37 which outputs a logical product of b2 and * c2, and a2 and *. An AND gate 38 that outputs a logical product with c2 and an OR gate 41 that outputs a logical sum of the outputs of the AND gates 34, 37, and 38 are provided, and the output of the OR gate 41 is the third bit s3 of the sum.

This equivalent-value 2-bit adder 14 has the same circuit scale as the 1-bit full adder 10 of FIG. 4 in spite of performing addition of upper 2 bits, and therefore the circuit scale is the same as that of the conventional one. It becomes 1/2. Further, carry c3 from the 1-bit full adder 12 to the 1-bit full adder 13 in FIG.
Since there is no need to wait for the confirmation of, the addition speed is about twice that of the conventional one.

The adder having the above configuration is used, for example, as an adder in an arithmetic logic unit (ALU) of a microprocessor. Since the ALU is well known, its description is omitted (for example, refer to "VLSI Computer Architecture" edited by Osamu Tomizawa, Shokoido).

[0019]

As described above, in the adder and the microprocessor using the same according to the present invention, the addition of the upper 2 bits is performed by the upper side bit calculating section and the lower side bit calculating section, and its configuration Has a circuit scale comparable to that of a 1-bit full adder, and therefore the circuit scale is about
Further, since it is not necessary to wait for the confirmation of the carry from the lower side of the upper 2 bits to the upper side, it is possible to obtain an excellent effect that the addition speed is about double that of the conventional one.

[Brief description of drawings]

FIG. 1 is a logic circuit diagram of an equivalent 2-bit adder according to an embodiment of the present invention.

FIG. 2 is a block diagram of a 4-bit adder using the equivalent 2-bit adder of FIG.

FIG. 3 is a block diagram of a conventional 4-bit adder.

FIG. 4 is a logic circuit diagram of a 1-bit full adder.

[Explanation of symbols]

 10-13 1-bit full adder 14 Equivalent 2-bit adder 20-22 Inverter 30-38 AND gate 40, 41 OR gate

Claims (3)

[Claims] 1. An adder for adding an augend of a value a whose upper two bits are equal to each other and an addend of a value b whose upper two bits are equal to each other, wherein When the carry is c, when one or three of a, b and c have the value 1, the value 1 is output as the lower side bit of the upper 2 bits of the addition result, and at other times, the value 0 is the lower side. Lower side bit calculation unit (20 to 22, 30 to 33, 40) that outputs as a side bit, and a and b both have a value of 1 or a value of 1 when a or b has a value of 1 and c has a value of 0. Is output as the higher-order bits of the higher-order 2 bits of the addition result, and the value 0 is output as the higher-order bits at other times.
8 and 41), and an adder. 2. The lower bit calculator calculates a value * a by inverting a value a and outputs a value * a, and a value b.
Second inverter (21) that inverts and outputs the value * b
And a third inverter (22) that inverts the value c and outputs the value * c, a first AND gate (30) that outputs a logical product of the value a, the value b, and the value c, and the value * a. A second AND gate (31) that outputs a logical product of the value * b and the value c, and the value * a
And a third AND gate (32) that outputs a logical product of the value b and the value * c, and a fourth AND gate (33) that outputs a logical product of the value a, the value * b, and the value * c, A first OR gate (4 that outputs a logical sum of outputs of the first to fourth AND gates)
0), and the higher-order bit calculation unit outputs a logical product of a fifth AND gate (34) that outputs a logical product of a value a and a value b and a logical product of a value b and a value * c. Sixth AND gate (37) and a seventh AND gate (38) which outputs a logical product of the value a and the value * c
The adder according to claim 1, further comprising: a second OR gate (41) that outputs a logical sum of outputs of the fifth to seventh AND gates. 3. A microprocessor using the adder according to claim 1 or 2 as an adder in an arithmetic logic operation unit.