JPS54130842A - Method address generator - Google Patents

Method address generator

Info

Publication number
JPS54130842A
JPS54130842A JP3895178A JP3895178A JPS54130842A JP S54130842 A JPS54130842 A JP S54130842A JP 3895178 A JP3895178 A JP 3895178A JP 3895178 A JP3895178 A JP 3895178A JP S54130842 A JPS54130842 A JP S54130842A
Authority
JP
Japan
Prior art keywords
generator
address
terminal
given
address generator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3895178A
Other languages
Japanese (ja)
Other versions
JPS5645229B2 (en
Inventor
Masao Shimizu
Takashi Tokuno
Koji Ishikawa
Naoaki Narumi
Osamu Oguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Advantest Corp
Nippon Telegraph and Telephone Corp
Takeda Riken Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp, Nippon Telegraph and Telephone Corp, Takeda Riken Industries Co Ltd filed Critical Advantest Corp
Priority to JP3895178A priority Critical patent/JPS54130842A/en
Priority to US06/026,246 priority patent/US4293950A/en
Publication of JPS54130842A publication Critical patent/JPS54130842A/en
Publication of JPS5645229B2 publication Critical patent/JPS5645229B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns
    • G01R31/31921—Storing and outputting test patterns using compression techniques, e.g. patterns sequencer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/31813—Test pattern generators

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To realize disuse of a linkage program and address high-speed generation by linking a address generator and a row address generator with each other by circuits. CONSTITUTION:An addition instruction and an enable signal are given to terminals 27 and 28 of column address generator 23 respectively from control circuit 20. At this time, though the addition instruction is given to terminal 27 of row address generator 24, the enable signal is not given to terminal 28. Consequently, generator 23 performs arithmetic operation to count up the address, however, generator 24 does not perform arithmetic operation. Comparator 21 detects the agreement between the output of generator 23 and the boundary value of register 19 and generates a coincidence signal. The coincidence signal is applied to terminal 19 of generator 24 and terminal 32 of generator 23, and the address of generator 24 is counted up by ''1'' to reset generator 23.
JP3895178A 1978-04-03 1978-04-03 Method address generator Granted JPS54130842A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3895178A JPS54130842A (en) 1978-04-03 1978-04-03 Method address generator
US06/026,246 US4293950A (en) 1978-04-03 1979-04-02 Test pattern generating apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3895178A JPS54130842A (en) 1978-04-03 1978-04-03 Method address generator

Publications (2)

Publication Number Publication Date
JPS54130842A true JPS54130842A (en) 1979-10-11
JPS5645229B2 JPS5645229B2 (en) 1981-10-24

Family

ID=12539498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3895178A Granted JPS54130842A (en) 1978-04-03 1978-04-03 Method address generator

Country Status (1)

Country Link
JP (1) JPS54130842A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5819955A (en) * 1981-07-29 1983-02-05 Toshiba Corp Picture memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5819955A (en) * 1981-07-29 1983-02-05 Toshiba Corp Picture memory device
JPH0375905B2 (en) * 1981-07-29 1991-12-03 Tokyo Shibaura Electric Co

Also Published As

Publication number Publication date
JPS5645229B2 (en) 1981-10-24

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