JPS54142955A - Syndrome generator circuit - Google Patents

Syndrome generator circuit

Info

Publication number
JPS54142955A
JPS54142955A JP5213378A JP5213378A JPS54142955A JP S54142955 A JPS54142955 A JP S54142955A JP 5213378 A JP5213378 A JP 5213378A JP 5213378 A JP5213378 A JP 5213378A JP S54142955 A JPS54142955 A JP S54142955A
Authority
JP
Japan
Prior art keywords
syndrome
codes
error correction
input terminal
via input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5213378A
Other languages
Japanese (ja)
Other versions
JPS5857782B2 (en
Inventor
Hidehiko Kobayashi
Hiroshi Ihara
Yukio Takahashi
Noboru Hagiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP53052133A priority Critical patent/JPS5857782B2/en
Publication of JPS54142955A publication Critical patent/JPS54142955A/en
Publication of JPS5857782B2 publication Critical patent/JPS5857782B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To obtain an integrated syndrome generator circuit which generates the syndrome from the information codes and error correction codes featuring different widths.
CONSTITUTION: The exclusive logic sum is secured for information codes (D0, D1, D2, D3) via input terminal 3 as well as for error correction codes C2 and C3 via input terminal 4, switch circuit 1 and signal line 10 respectively. Then the exclusive logical sum operation is given between the above exclusive logical sum result plus error correction codes C0 and C1 applied via input terminal 5. Thus, syndrome codes S0 and S1 are delivered through output terminal 7, and at the same time syndrome S2 and S3 are delivered through output terminal 8 respectively. This operation features as S0=D0+D2+D3+C0, S1=D0+D2+D3+C1, S2=D1+ D2+C2 and S3=D2+D3+C3.
COPYRIGHT: (C)1979,JPO&Japio
JP53052133A 1978-04-27 1978-04-27 Syndrome generation circuit Expired JPS5857782B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53052133A JPS5857782B2 (en) 1978-04-27 1978-04-27 Syndrome generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53052133A JPS5857782B2 (en) 1978-04-27 1978-04-27 Syndrome generation circuit

Publications (2)

Publication Number Publication Date
JPS54142955A true JPS54142955A (en) 1979-11-07
JPS5857782B2 JPS5857782B2 (en) 1983-12-21

Family

ID=12906361

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53052133A Expired JPS5857782B2 (en) 1978-04-27 1978-04-27 Syndrome generation circuit

Country Status (1)

Country Link
JP (1) JPS5857782B2 (en)

Also Published As

Publication number Publication date
JPS5857782B2 (en) 1983-12-21

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