JPS5819955A - Picture memory device - Google Patents

Abstract

PURPOSE:To improve the efficiency of operation to make them high-speed, by generating a memory address in the hardware construction and designating them with a relative address. CONSTITUTION:A control signal is inputted to a terminal CM of an operator 1 through a control bus 4 to designate an operation. The address signal of a picture memory 3 is inputted to a terminal A through an address bus 5, and the address modification signal outputted from an address modification register 2 is inputted to a terminal B. The address modification register 2 receives data from a data bus 6 and the control signal from the control bus to send address modification data to the address operator 1. Various address calculations are performed in the memory address operator 1 by inputted signals, and the address signal is sent to the picture memory 3 through a memory address bus 7 from a terminal Q.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a drawing device for use in an I-1 proverb recognition device and the like.

Conventionally, addresses for image printing devices have been generated by directly instructing a mail address using a program program, as shown in EK 1, and for certain trout, counting up by +1 from the directly instructed value, as shown in Fig. 2. etc. are being implemented.

Conventionally, image memory devices have had the following limitations and requirements. That is, (1) It is a two-dimensional data array shown in Figure 3 of Image Data Company, but a one-dimensional data array shown in Figure 3 of Image Data Company,
It is a structure. For this reason, in the past, two-dimensional data was continuously generated and written by calculating in a programmer and specifying the results, which was difficult to achieve at high speed.

(2) It takes a certain amount of time (varies depending on the device) for the memory element to become readable and writable after address specification, resulting in wasted time after address specification (address generation after read and write). There is no wasted time if you process the previously read data and then execute the same cycle.)

(3) Since data in the l1ill memory is processed by repeating reading and writing several times, address generation needs to be simple and fast.

(4) An image memory device that stores a large amount of private data must be able to expand its memory capacity.

(5) It is desirable to be able to generate a new address signal when data at a certain address is read and written to the same address, and vice versa.

This invention has been made in view of the above circumstances, and its purpose is to provide an image memory device that can read and write -dimensional array data as if it were two-dimensional array data, easily and at high speed, for a large group of image data. It's about doing.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 5, 1- is a memory address calculator, 2 is an address modification register, and sld image memory. Signals are input to the address calculator 1 and the address modification register 2 from a computer and other control devices. That is, a control signal is input to the CM terminal of the arithmetic unit 1 via the control path 4 to designate an operation. *The address signal of the image memory 1 is input to the m child via the address bus 5,
Furthermore, the address modification register 2 receives the data from the data bus d and the control signal from the control bus, and inputs the address modification signal to the B terminal. Send modification data to address calculator I.

Memory address arithmetic unit xFi performs various address calculations on input signals,
An address signal is sent to the image memory 3 via. Further, read signals and write signals are sent from the control device to the image memory 3. Zero image data is transmitted via the image data path 8 in accordance with the address signal created as described above.

9 is a decoder, and the control signal is inputted to this decoder 9 together with the L1 write signal and read signal, and the transmission of the p1 image data is completed, and this completion signal specifies the designation by the read and write post-calculation commands. If so, a memory address data latch signal is output to address calculator l.

Then, this address calculator Z calculates the memory address again, and preparations are made for the next data transmission.

Figure jI6 shows a specific configuration of the memory address calculator 1, in which registers 10. It is composed of arithmetic units xrl and vzipfirzK. The following table shows an example of the arithmetic functions of this memory address arithmetic unit I.

Next, an example of a projection method for image processing will be described in detail with reference to FIG. 97. I! When compressing the data by converting the two-dimensional data image r-ta group (M+1)(N+1) shown in Figure 8 into -dimensional data using a projection method, the X-ring projection image P(1) UPI (I)=up (I+(
N+1) J) tona p1 image J scale 0 memory address! must be generated by the calculation x=I+(N+1)J&. Similarly, Y-axis projection PY(J)
Fi, where I; X-axis projection @Xth JAY-axis projection image JIIth MIX Number of image memories in the X-axis direction N; Number of image memories in the Y-axis direction It can be seen that the sum of the O-M image data is calculated without addition.

Also, X-axis image i;1. 0 because we added N+14D value
By calculating the sum of ~N image data], in order to store the carry from the upper digit of the adder in the memory address calculator 1 at the time of the Nth addition, this is transferred to the lowest digit. By adding this, the memory address modification shown in FIG. 8 is possible.

In other words, in this invention, unlike the conventional method of specifying a memory address using an absolute address, a method of specifying a memory address using a relative address has been adopted in a hardware configuration, which improves operational efficiency and speed. It is possible to

Generally, the image memory has a large capacity and is not subject to processing, but only the part shown by P in Figure 10 is processed, and the part shown by Q, which is slightly shifted from this position, is processed. The main method is to move the target of processing sequentially (specified by relative address). Therefore, programs for pattern recognition and image processing become simpler.

After transmitting the image data, the next message address is calculated and set by the hardware (bytes). It was,
Since it is a relative address system, the memory capacity can be expanded regardless of the size of the memory address bus.

In addition, since the memory address is generated by hardware, the number of Stellar 1s in the program is reduced and the processing speed is improved.

Furthermore, since it is possible to specify in a program that a memory address is calculated when reading and writing to the image memory, flexible address modification is possible.

Figure 10 shows a one-dimensional memory that can be specified using two-dimensional values (x, y). 2 shows the address modification register in the vertical (G) direction, and 2Bfd shows the address modification register in the horizontal (A) direction. .

淘、This invention is that the video signal of the TV program, etc. is about 1
Since it is a high-speed signal of 00 ns@@/pixel, a high-speed memory is required, but it can be used as temporary storage (high-speed image memory buffer). Additionally, it can be used as an image memory of an image data processing device.

[Brief explanation of the drawing]

Figures 1 and 2 are block diagrams showing conventional memory address generation methods, Figure 3 is a diagram showing one row of memory elements, and Figure 4 shows the arrangement of memory elements as an arrangement of two-dimensional image data. FIG. 5 is a block diagram showing an embodiment of the present invention; FIG. 6 is a block diagram showing an enlarged part of the memory address calculation unit in FIG. 5; FIG. A diagram showing an example of a designated route, IK9 diagram is a diagram showing the extraction of a partial part of the image memory and movement of the extraction position,
FIG. 10 is a block diagram showing another embodiment of the invention. 1.../497 address arithmetic unit, 2... Address modification register, #-... Image memory, 4... Decoder. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. An image printing device comprising: an address arithmetic unit that receives input information and generates an address signal; and at least one address modification register that outputs an address modification signal to the address arithmetic unit.