SU1290399A1 - Device for displaying information - Google Patents

Description

one

The invention relates to automation and computer technology and can be used to generate graphical images of seismic information on the screen of a cathode ray tube, which allows seismic information to be represented by methods adopted in geophysics (variable amplitude, variable area, variable density, etc. ).

The purpose of the invention is to increase the speed of the device.

FIG. 1 is a block diagram of the device; in fig. 2 shows the types of seismic images used in the processing of seismic information; in fig. 3 is a block diagram of synchronization; in fig. 4 - control unit;

12903992

The synchronization unit 2 generates a clock series, synchronization signals and Gsgeni, used to control the digital-to-analog converter. The digital-to-analog converter 3 is designed to form an analog video signal input to the display unit 4 and is a monitor with a raster scan controlled by a video input.

The control unit 5 decrypts the information from the device input, stores it in the corresponding registers, generates data and generates control signals for recording information in the unit

memory; the memory block and the code converter generates signal tags; the memory block and the code converter generates the signal of FIG. 5 — address generation unit; in fig. 6 is a timing diagram of the control unit 20 units forming the operation of the device in the external address mode, provides an analysis of a ready-gather gather; in fig. 7 shows the temporality of the device for receiving the ocher and internal inner information and generates gating signals to ensure the operation of the entire device.

The memory unit 6 is designed to store information to be displayed in unit 4.

Switch 7 serves to pass through 30 neither to information block 8 contained either in memory block 6 or in a register.

Block 8 is for fast

    conversion in tempo output to

the first switch 15, the first counter 16, 35 the screen of the display unit) information element OR, 17 and the second register 18. according to the law specified by the operator

chart in the mode of smogram.

The device contains the first register 1, synchronization unit 2, digital-analog converter 3, CRT display unit 4, control unit 5, memory unit 6, third switch 7, main memory unit 8, address generation unit 9, fourth counter 10, the second switch 11, the converter 12 codes, the third counter 13, the second counter 14, synchronization unit 2 includes a master oscillator 19, a counter of 20 points, a decoder 21, a counter of 22 lines.

The control unit 5 contains the input decoder 23, the switch 24, the register unit 25, the decoder 26 of the control, the repetition counter 27, the unit 28 for the operation of the counters 29, the decoder 30,

Block 9 formation of addresses, switch. 31, registers of 32 addresses and modifications, switch 33, adder 34, output register X 33, commutator 50 36, registers of 37 addresses and modifications 37, switch 38, adder 39, output register Y 40, register 4 of the start address, counter 42 regeneration addresses5 output switch 43, 55 register 44 addresses.

Register I is designed to receive and store information from the input of the device.

memory; the memory block and the code converter generates the control signals of the address formation blocks, provides an analysis of the device readiness for receiving the contour of the device.

The address generation unit 9 serves to form the write addresses.

(reading), as well as to form screen registration addresses and memory microchips (when using memory 6 in memory block 6 of a dingshic memory requiring cyclic confirmation of its state).

The counter 10 is designed to generate and store information on the amount of change (modification) of the address or on the number of write cycles required for complete processing of the received information.

The switch 11 transmits the information ifliio to the address input of the converter 12 from three directions: the first register, the code converter and the third counter (address).

The 12 kodo-3 converter is intended for storing and recording information.

The information on the type and law of seismic information conversion is a storage device on static memory microcircuits that have a short sampling time, which is necessary for fast processing of incoming information.

Counter 13 (addresses) provides the formation of the current address when writing (and reading) information in npeo6pa

Appeal 12.

The counter 14 generates the data recorded in the memory block 6 and determining the intensity or color of the information output to the block 4.

The third switch 15 transmits information from the counter 14 or directly from the register 1.

The counter 16 is designed to control the counter 14 when converting the 20 count, the location on the screen is 35

information with a sign of Level.

Element 17 provides for recording information into counter 16 by the gate from control unit 5 or by counter overflow.

 Register I8 is used to store the minimum change in the input data, causing a change in the data generated by the counter 14 and recorded in memory block 6,

The device allows to form, both offline and in communication mode with the computing complex, everything you see: the seismic information displays shown in FIG. 2

The device operates in four modes: a seismogram of externally single-phase parametric right; seismogram is externally one-parameter with conversion; seismogram is external two parameter; seismogram internal

The seismogram is externally one-parameter pr ma.

The mode is intended to convert the input information array into a graphical form according to (D) or (D) and record the obtained results into a memory block. The conversion functions are set by the operator and stored in the converter 12.

The mode is characterized by the fact that data that does not undergo preprocessing in block 8 is received from the device input. To work in this mode, the following service information is received from the input:

written information;

- the magnitude of the change (modification) of the addresses of the recording in the X and Y coordinates after writing to the memory block 6

25 of each next point, (the starting addresses of the record and the modification of addresses of the record by the X and Y coordinates are recorded in registers 32 and 37 respectively

-the initial address of the Converter 12, recorded in the counter 13;

The conversion law data written to block 12, which have three parameters: the first one sets the data code to be written

in block 6 of memory and, ultimately, determines the color of the seismogram displayed on the screen; the second one indicates the type of transformation, i.e. determines which element (point or vector) should be formed on the screen; the third one sets the length of the vector (with the second parameter Vector) or the value of the address modification (with the second parameter Point);

. - a sign of the change of the first parameter (Level or Amplitude) and the speed of this change. Signs are entered in register 18 along the gate formed in control decoder 26. The same strobe passes through the element OR 17 and records the magnitude of the rate of change in counter 16.

Next, we consider the operation of the device according to the diagram of FIG. 6. The diagram corresponds to the operation of the device during the formation of a vector element and the priority transformation channel along coordinate X. When the data is at the first point of the initial information

40

45

50

55

stre 1;

- indications of the mode of operation (External, Pr), which are recorded in one of the registers of the register 25 block. They control the switch 24, which passes to the output the information coming from the switch 15, and the switch II, which connects to the address input of the converter 12, data stored in the Priority register, which is entered into one of the registers of the register 25 and determines coordinate relative to which the transformation will occur

-the initial addresses of the records in the X and Y coordinates, which will be

recorded in memory block 6 first point, i.e. determined at the end

five

0

written information;

- the magnitude of the change (modification) of the addresses of the recording in the X and Y coordinates after writing to the memory block 6

5 of each next point, (the starting addresses of the record and the modification of addresses of the record by the X and Y coordinates are entered into registers 32 and 37, respectively);

-the initial address of the Converter 12, recorded in the counter 13;

The conversion law data written to block 12, which have three parameters: the first one sets the data code to be written

in block 6 of memory and, ultimately, determines the color of the seismogram displayed on the screen; the second one indicates the type of transformation, i.e. determines which element (point or vector) should be formed on the screen; the third one sets the length of the vector (with the second parameter Vector) or the value of the address modification (with the second parameter Point);

. - a sign of the change of the first parameter (Level or Amplitude) and the speed of this change. Signs are entered in register 18 along the gate formed in control decoder 26. The same strobe passes through the element OR 17 and records the magnitude of the rate of change in counter 16.

Next, we consider the operation of the device according to the diagram of FIG. 6. The diagram corresponds to the operation of the device during the formation of the vector element and the priority transformation channel along the X coordinate. When the data is at the first point of the initial information

0

five

0

five

the array is fed to the device input and to the register, the signal from the input decoder 23 starts the processing unit 28 (0 and generates a signal (Tycf.aap) for switching the output switch 43, which until this moment passes to the memory unit 6 the regeneration address, provided the output of the information recorded in memory block 6 to the passage of the recording address coming from output registers 35 and 40; In the control decoder 26, the signals ON / MOD and O / P are generated, providing the output of the registers 32 and 37 appropriate starting x addresses or address modifications. The information recorded in register I goes through the inverter register of register 25 and the switch 11 to the address input of the converter 12, from the output of which the first parameter is written to the counter 14, the second parameter goes to the address generation unit dp control - to mutators 23 and 38. If this is the Vector parameter, then the switches pass information from registers 32 and 37, if the Point is the information arriving

from the output of the counter 10.

In the control decoder 26, signals Uyx are generated and, and according to which the starting addresses of the record are written to the output registers X 35 and Y 40

Gig 6), which by the gate Reg. as it moves away from the axial

are entered in address register 44 and are fed to the input of memory block 6. The output of the counter 14 through the switch 15 and the switch 24 is fed to the data input of the memory block 6.

In the trigger circuit, a signal is generated,. allowing to set at the set address the information at the input of the memory block. Simultaneously with the record on the adder of the priority channel 34 (in our case, the priority coordinate X), the address contained in the output register X 35 is added and the address is modified by the X coordinate received through the switch 33, i.e. the new address is defined . For the next Reg Regr gate, the address found is rewritten via the output switch 43 to the address register 44.

At the same time, the content of counter 10 is reduced by one. Starts

fO

5 ZO

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from the second write cycle to the memory block 6. The device operates as described) (a vector is formed in the horizontal direction on the screen) until an overflow pulse arrives from counter 10. cr. In this case, the processing unit 28 (T 0, T ,, p, O) is reset, and a non-priority channel (on the adder 39) produces an ar (the initial address on the Y coordinate stored in the output register Y 40 with the value in the register of modification of the record by the coordinate Y. 5 The result obtained by pulse 1 is entered into the output register Y 40 and simultaneously into the register of the starting address of the record Y, located in 37. The device is ready to receive the next data from the information input.

This memory for block 6 of memory formed in counter 14, in the example described, can. be unchanged and repeat the contents of the first parameter of the converter 12, if the sign Amplitude is recorded in register 18. It blocks counter 16, which results in the absence of a signal from its output. Therefore, the contents of counter 14 are unchanged. However, the interpretation of seismic information is facilitated if the color of the seismogram depends on the size of the input data, i.e. measured20

0

5 5

lines. Such a law of color change is achieved if the Level attribute is used. Register 18 also records how many clock cycles the color should change. those. the rate of color change depending on magnitude is indicated. rejection. The counter 16, into which the code in register 18 was entered before starting work, changes its value (decremented by one) at the end of each write cycle. As soon as counter 16 takes on a value equal to zero, the impulse of the overflow pulse, 0 forming at its output, adds one to the code stored in counter 4.

In regsm Level, at the start of operation, a certain value is entered into the counter 14 (n, Srimer, zero), which begins to increase as the vector is displayed.

The seismoamma is externally one-parameter with transformation.

Work in this mode is similar to that described with the difference that the data of the original information array from register 1 is fed to switch 7 from whose output through block 8 and switch 11 they are fed to converter 12 of codes. Thus, the data of the input information array is fed to the address buses of the converter 12 after the prelimi- nary. Noah processing.

Seismogram is externally two-parameter,

Characterized by the fact that each of the data of the input information array contains two variables, one of which is in the device

-

By the Reg.adr gate, they are rewritten to address register 44 and fed to memory block 6 (Fig. 1). There is a reading from the memory block of the first point of the information array. At the same time being found

20

is converted to a deviation value, and the second determines the color of the data on the screen. The operation of the device is similar to that described with the exception that the first variable (recorded in the low byte of the input word) of the next readout address of the next point informs through the switch 11 to the address mation array by adding the converter 12 input, and the second - on adders 34 and 39 (FIG. 5) the corresponding values of the current starting addresses stored in 35 and 40,

The mode is intended for reading up to 30 with the contents of the registers 32 and 37 of the moss data stored in the read specification on the X coordinates of block 6 by addresses. | , their conversion into graphical form according to (D) or (D) and recordings obtained through switch 24 on memory block 6. Seismogram internal

readable results for addresses B- {B; . Here, the conversion functions are located in the converter 12.

The difference from the described modes of external Y, respectively. The signals Ujj and Well are written to write the obtained value into output registers 35 and 36-25 and the signals x and y to enter it into registers 32 and 37 of the initial reading address along the coordinates X and Y, respectively.

The signal ZP / CHI takes the value of their seismograms in that, 0 ZP and from registers 32 and 37 initial that when processing each point of the source addresses of the recording, the recording address is entered into the output registers of which information array 35 and 40. By

End of THT pulse indicating that the reading cycle is over, data from 45 memory block 6 (Fig. 1) through the first switch 7, RAM 8 and the second switch 11 arrive at the address input of the converter 12 codes, from the output of which the first parameter is written to the second the counter 14 and through the third switch 15, the switch 24 is fed to the input of block 6, as data.

It is necessary to organize a reading cycle from memory block 6. In addition to the service information described by Bbmte: initial reading addresses in X and Y coordinates; modification of the reading addresses in the X and Y coordinates (this information is written into the address registers and modifications 32 and 37, respectively); 50 number of repetitions, determining the value (amount of data) of the array being processed (this information is recorded in the repetition counter 27 of the control unit 5).

Let us consider the operation of the device according to the timing diagram of FIG. 7, which corresponds to the processing of the data of the information array during the second period, which must be recorded.

The second parameter (in our case, its Point) enters the address generation unit and sets the switches 33 and 38 (Fig. 5) to the position where the input of the priority channel adder 34 enters

ten

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The transformer point and

priority canape X.

In the latter case, when the service information arrives at the input of the device, a trigger is generated, on which the mining unit 28 is cocked. . one . Sub-synchronization to the clock pulses of the memory unit 6 is performed and the switching trigger of the address tvBp is turned on by the i-switch 43 switches to pass addresses from. output registers 35 and 40.

The write pulses are formed in the output registers X and Y (U.and,), according to which the starting addresses of the read addresses in the X and Y coordinates are written in registers 35 and 40, respectively.

By the Reg.adr gate, they are rewritten to address register 44 and fed to memory block 6 (Fig. 1). There is a reading from the memory block of the first point of the information array. At the same time being found

20

25 read addresses of the next point of the information array by adding on the adders 34 and 39 (Fig; 5) the corresponding values of the current starting addresses stored in 35 and 40,

50

to be recorded.

The second parameter (in our case, its Point) enters the address generation unit and sets the switches 33 and 38 (Fig. 5) to the position where the input of the priority channel adder 34 enters

formation from the first counter 10 (Fig. 1). This counter records the third parameter, the determined value of the deviation of the formed element (point) from the vertical axis, determined by the value of the starting address X. This parameter, by the priority coordinate X, is summed with the starting address X 35 (Fig. 5) located in the output register and the result is rewritten again to the output register X 35. Further, via the Reg.adr gate, it is rewritten to register 44 and fed to memory block 6 {FIG. 1}. The recording cycle begins. At the same time, the non-priority coordinate Y is the addition of the starting address of the record Y stored in the output register Y 40 (Fig. 5) with the value of the record modification register Y 37 and the result after writing to the output register Y 40 is rewritten into the register of the initial address 37,

The CP / TH signal is set to the BT position and from the registers 32 and 37 of the initial reading addresses in the X and Y coordinates, the information about the reading address of the next point is written to the output registers X and Y 35 and 40.

The first point of the information array is processed.

The next reading cycle begins. The device operates until those times until the counter 27 repeats (Fig. 4), decreasing its value by one for each impulse. End THT, reaches zero. This indicates that all the points of the information array set to transform have been worked out. Reset

block 28 mining (O, T

Ler AER

0)

and the device finishes work. Starting the device can be carried out only on arrival at the output of the device of the next sign. Starting in a word with service information.

Claims (1)

Invention Formula A device for displaying information comprising a first register, the input of which is the device input, a synchronization unit, the output of which is connected to the first input the course of which is connected to the display, the control unit whose output is connected to the memory unit, the second is connected to the output of the addresses, the first is connected to the second in the control, the output and the input are connected to the first inputs of the control unit, the third input operating memory, about the fact that, with no speed, the mouth contains a second register, a first counter, the first coil of which is connected to the input of the control unit, three connected to the second switch, the code, the second output to the second inlet and addresses, and the fourth turn of which is connected to the second input and the third input without the addresses, the third input of which is the connection of the memory unit, and you are the input of the operating element OR, the first input connected to the output and the second input, the second input of the second, the first inputs of the third and second register, the second and second counter of the commutator, the code block element, the fourth of the third switch and the common memory are connected by the output of the control register unit connected by the input of the second switch by the inputs of the third counter register and third I and the third switch with 0 RAM with the second input of the second to the second input of the digital input form, the third one in the code gate is connected digital-to-analog converter, you are the house of the second counter. five five 0 five the stroke of which is connected to the input of the display unit, the control unit, the first output of which is connected to the first input of the memory unit, the second input of which is connected to the output of the address generation unit, the first input of which is connected to the second output of the control unit, the output and input of the first register are connected to the first and the second inputs of the control unit, respectively, the third input of which is connected to the output of the synchronization unit, and the operational memory unit, which differs from the fact that, in order to increase the speed of the device, it contains the second register, the first counter, the second counter, the first switch, the output of which is connected to the fourth input of the control unit, the third counter connected in series, the second switch, the code converter, the second output of which is connected to the second input of the address generation unit, and the fourth counter, outputs which are connected, respectively, to the fifth input of the control unit and the third input of the address generation unit, the third switch, the first input of which is connected to the output of the memory unit, and the output - with the first input of the RAM, and the OR element, the first input and output of which are connected respectively to the output and the second input of the first counter, the second input of the second switch, the first inputs of the third counter and the second register, the second inputs of the first and second counters, the first com1 -1 of the switch, the OR element, the code converter, the fourth counter, the third switch and the RAM block are connected to the second output of the control unit, the output of the first register is connected to the third input of the second switch, the second inputs the third counter and the third register and the third inputs of the first and third switches, the output of memory block 0 is connected to the fourth input of the second switch and the second input of the digital-to-analog converter, the third input of the code converter is connected to the third input 0 ch ch szh zhz one d L J6i) j (7 Awa go  tf A AMFXC -rf. fl. O & So & OS Lig g 3) j 0 I I: ..I .421 A-5.5 . cjfft / ff.3 I I Vy & e / fmi7p / frrC7 / fC / I   off / y. P efl. cr (pi / ff.6 eri a. five P Jt R J l Editor K. Voloshchuk Compiled by S. Grishin Tehred V. Kadar Order 7909/51 Circulation 455 VNIIPI State Committee CGGP for inventions and discoveries 11.3035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Proofreader A, Ilyin Subscription