SU1259217A1 - Digital interpolator - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in software control systems and control machines, in particular in devices for displaying graphic information. on the cathode ray tube screen or on the plotter. The purpose of the invention is to increase the speed and simplify the device. The digital interpolator contains five registers, a comparison unit, a permanent memory unit, three multiplexer units, a pulse generator, two triggers, a delay element, AND, 2I-OR elements, three counters, and two decoders. This digital interpolator allows increasing the productivity of information preparation for control programs of devices with numerical software, speeding up the output of graphic information to display devices. At the same time, the uniform arrival of pulses along the coordinates allows refusing additional nodes for modulating the brightness of a CRT beam, depending on the increment values, and improves the dynamic characteristics of software systems. 2 Il. (Ls

Description

The invention relates to automation and computer technology and can be used in various software control systems and control machines, in particular, in devices for displaying graphical information on an electron beam screen (CRT) or on a plotter.

The purpose of the invention is to increase

speed and simplify the device.

Figure 1 shows the block diagram of the interpolator; FIG. 2 shows an example of a direct approach.

The digital interpolator contains the first 1, second 2, third 3 and fourth 4 registers, the fifth shift register 5, the comparison block 6, the permanent memory block 7, the first 8, the second 9 and the third 10 multiplexer blocks, the P pulse generator, the first 12 and second 13 triggers, delay element 14, first 15, fourth 16, sixth, third 18, fifth 19, second 20 and seventh 21 elements AND, third 22, first 23 and second 24 pulse counters, third 25, first 26 and the second 27 decoders, the first 28 and the second 29 elements 2I-OR.

The operation of the device is based on the fact that any direct can be presented not as a continuous sequence of mathematical data; points, but as a region formed by a set of raster elements directly adjacent to one another. A set of periodically repeating numbers, each of which indicates the number of raster elements in a row (column), is called the front characteristic of the facade (X (p). The minimum length of the straight line segment on which its facade characteristic is detected is considered the basis full image direct. In this case, the basis of the full image direct consists of a sequence of only two numbers differing by one.

At the input of the device, registers 1 and 2 receive the values of DH and 4Y pr, which need to be interpolated. The outputs of registers 1 and 2 are connected to the address inputs of the Permanent Memory 7. The values of the numbers that make up the characteristic F5 are set at the outputs of the Permanent Memory.

20 30

2592172

the garden of the direct and the sequence of these numbers in the formation of the basis of the full image of the direct. The Start signal, through blocks 8 and 9 of multiplexers, under the control of block 6, the comparison values ХХ and А Y, is entered into counters 23 and 24 pulses. Comparison unit 6 has two outputs. For example, if aX uY, then the first output is high, the second low, with & X AY the first output low, and the second high. In this case, a large coordinate (long axis) is recorded in the pulse counter 24, and a smaller coordinate (short axis) is recorded in the pulse counter 23. By the start signal, the pulse counter 22 is reset and, synchronously with the operation of the clock pulse generator, the first trigger 2 is set to

one.

The next clock pulse sets 1 second trigger 13, passes through the first element 15 and writes the third 3, fourth 4 and fifth 5 registers to the information from the outputs of the permanent storage device. In the third 3 and fourth 4 registers, the numbers defining the characteristic of the façade of the façade are recorded, and in the shift register 5, the sequence of tracing the façade numbers to form the basis of the full image of the façade. In this case, the indicated sequence of following the numbers of the facade is repeated until the end of the interpolation direct with the given facade.

A clock pulse that is delayed by one half of the period following the delay element 14 passes through the element 17, the element 19 and enters the pulser at the input of the control of the parallel recording. On the input of the third block of 10 multiplexers (the inputs of the parallel recording of the pulse counter 22 pulses) one of the numbers of the forward characteristic of the façade is determined, which is determined by the high bit of the shift & 5 register. For example, if the older bit of the register 5 is 1 , then at the output of block 10 multiplexers - the first number of the characteristics of the front facade, if O is the second number.

Suppose we need to screw in the straight AX 5, UY 2.

Characteristics of the facade of such a direct will be 2, 3.

The number of 5 is recorded in the pulse counter 24 (pain coordinate), the number 2 in the pulse counter 23 (the smaller coordinate) 5.

The impulse counter 22 must first work out 2 counter impulses (the value of the first number of the facade) and give the impulse to the end of the count (for example, generate a transfer signal).

The first pulse from the element And 16 passes to the counting input of the counter 22 and the element And 18.

Since the value of the counter 24 and G5 pulses is not zero, there is a resolution from the decoder 27, the pulse from the output of the AND 18 element is fed to the input of the counter 24, subtracting the unit from its content, and also passing through the element 2Y-OR 28 to device output.

The second impulse passes to counter 22, forms the end-of-count impulse, and to element 18, from the output of which 25 pulses go to the input of counter 24, subtracting one from its content, and passes through element 2I-OR 28 to the output of the device .

The signal End of the Counter from the counter 22 goes to the input of the element I 20, from whose output (the resolution of the decoder 26 determining that the contents of the counter 23 is not zero) enters the input of the counter 23, subtracts one from its content, and also passes through the element 2И-И1Ш 29 to the device output.

The signal end of the counting also enters the register 5, making it shift. At the output of multiplexer unit 10, the following number of characteristics of the façade is set (in our example, the requirement of counting in

counter 22, equal to 3).

-45

Since at the output of the decoder 25, the decrypting state of the counter 22, there is a resolving urshen, a pulse on the element AND 1 7 delayed relative to the main pulse for half a period, passes through the element And 19 and loads the count 22.

The next three clock pulses are sent to the counting input of the counter 22, through the element 18 and 18 to the output 55 of the device (block 28) and subtract 3 ones from the counter 24, set its value equal to zero.

35

40

five

ten

G5 0

five

about

five

0

five

0

The third clock pulse of this account forms on the code of the counter 22 a signal of the end of the account, which passes through the element I 20 to the input of the device (block 29) and subtracts one from the contents of the counter 23. The value of the counter 23 is set to zero.

Since the permissive levels are set at the inputs of the AND 2I element (the values of the counters 23 and 24 are equal to zero), the pulse from the output of the element AND 17 rushes through the element 21 and sets triggers 12 and 13 to O.

The interpolation process is over. At the output of the device, 5 pulses (X) passed through block 28, and 2 pulses (Y) passed through block 29.

As can be seen from the description of the operation of the device, its operation algorithm is very simple and does not require additional high-speed computing blocks, adders, etc. This greatly simplifies both the device itself and its maintenance during operation of the design.

The speed of the interpolator coincides with the frequency of the generator of clock pulses and is limited only by the element base used.

This makes it possible to increase the productivity of preparing information for control programs of devices with numerical software, to accelerate the output of graphic information to display devices. At the same time, the uniform arrival of pulses in co-ordinates makes it possible to refuse additional nodes for modulating the brightness of a CRT beam, depending on the increment values, and improves the dynamic characteristics of software systems.

The quality of the image on the CRT screen is also enhanced by the best dynamic properties of the interpolator.

Claims (1)

Formula invented and A digital interpolator containing the first, second and third registers, a comparison unit and a pulse generator connected in series, the first trigger, the second trigger, the first element AND and the fourth register, and the second, third, fourth, fifth and sixth elements AND, first, second and the third pulse counters, distinguished by the fact that, five in order to improve speed and simplify the interpolator, a permanent memory block, a fifth register, three multiplexer blocks, the seventh AND element, a delay element, three decoders, and two 2I-PI elements, which are connected to the digital interpolator outputs, the first inputs to the outputs of the comparison unit and the first inputs of the first and second multiplexer blocks, respectively, the second inputs to the outputs of the second and third And elements, respectively, and the first inputs of the first and second pulse counters, the second entrance which are connected respectively to the outputs of the first and second multiplexers, the third inputs to the second input of the first trigger, to the Start input of the digital interpolator and to the first input of the third pulse counter, the outputs of the first and second pulse counters are connected to the inputs of the first and second decoders, respectively, the first the outputs of which are connected to the first inputs of the second and third elements respectively1B And, the second input of the second element And is connected to the first output of the third pulse counter with the first input of the fifth register, the second input of which is connected to the first output of the permanent memory unit, the third input to the first input of the third register, and vrsod to the first input of the third multiplexer unit, the second input of which is connected to the output of the fourth register , the third input is with the output of the third register, and the output is with the second input of the third pulse counter connected by the third Jq 0 5 0 five 0 176 input to the output of the fourth element I and to the second input of the third element I and the fourth input to the output of the fifth element I, the first input of which is connected to the output of the third decoder connected by the input to the second output of the third pulse counter, the second input of the fifth element I connected to the output of aiecroro element I and to the first input of the seventh element I, the second inputs of which are connected to the outputs of the first and second decoders, and the output to the third input of the first trigger and the second input of the second trigger, the third input of which is connected n to the output of the pulse generator, to the second input of the first element I, to the first input of the fourth element I and through the delay element to the first input of the sixth element I, the second input of the sixth and fourth elements I connected to the second output of the second trigger, the output of the first trigger connected to to the third input of the first element And, the output of the first register is connected to the first input of the first and second multiplexer blocks, to the first input of the comparison unit and to the first input of the permanent memory unit, and the output of the second register to the second input of the first second and second multiplexer units, to the second input of the comparison unit and -to the second input of the permanent memory unit, the inputs of the first and second registers are connected respectively to the first and second inputs of the digital interpolator, and the second elevators of the fixed memory unit are connected respectively to the second the inputs of the third and fourth registers.