SU941987A1 - Device for reproducing graphic data on cathode ray tube screen - Google Patents

Description

The invention relates to automation and computing and can be used in output devices and visual display of graphic information.

A device for displaying graphical information on a cathode-ray tube screen, comprising a vector generator connected to a deflecting system, registers of variables X and Y, and increment registers in X and Y connected to the address register and command register, control unit, memory and luminance register uj

The drawback of the device is the low accuracy of reproduction of information on bodies moving at high speed.

Closest to the proposed technical solution is a device for displaying graphical information on the screen of a cathode ray tube, containing

digital-to-analog converters in X and Y coordinates connected to a deflecting system, a light pencil connected to shapers of codes in X and Y axes connected respectively to a syllable former in the Y axis and a comparison unit in the X axis connected to the block a communication unit and a memory unit associated with the syllable registers on the X and Y axes, a control unit connected to the word register on the X axis and through a reversible counter of the X coordinate to the digital-to-analog converter on the X coordinate, increment adders, subtraction counter and adder coordinates Y moreover, the input of the subtracting counter is connected to the syllable register along the X axis, and the output and its other input are connected to the control unit; increment adders are connected to the syllable register along the y axis, the control unit and the adder of the y coordinate associated with the syllable register along the V axis, the control unit and the t coordinate analog-to-analog converter. A disadvantage of the known device is an abrupt movement of the image when displaying information about bodies moving with high speed, which reduces the accuracy of reproduction of information and worsens the reproduction of it by the operator. The purpose of the invention is to improve the accuracy of the device when reproducing visual information about bodies moving with great speed. The goal is achieved by the fact that a device for displaying graphical information on a CRT screen containing a communication unit with a computer, a sum storage unit, a control input which is connected to the corresponding output of the control unit, and digital-to-analog converters along coordinates X and Y, the outputs of which are connected to the deflection system of a CRT, the inputs of the digital-to-analog converter on the X coordinate are connected to the outputs of the variable registers on the X coordinate and the increments on the X coordinate, and the inputs of the D / A converter the Y-axis caller - respectively with the outputs of the variable registers and the increments by the Y-coordinate, the information inputs of the increment registers by the X and Y coordinates are connected to the outputs of the corresponding increment adders by the X and Y coordinates, and the control inputs of the increment register by the X and Y coordinates and registers variables along the X and Y coordinates — to the corresponding output of the control unit; it contains three counters of shift pulses, the control inputs of which and the outputs are connected to the corresponding –outputs and inputs of the control unit; Viga, which is connected to the installation input of the first shift pulse counter, scale registers by X and Y coordinates, the outputs of which are connected to the installation inputs of the second and third shift pulse counters, respectively, the address counter, whose input is connected to the corresponding output of the control unit, blocks the memory of variables and increments, the control inputs of which are connected to the corresponding output of the control unit, and the first information inputs to the first information input of the memory block of the sums and the output of the counter the addresses, the first switch, the information inputs of which are connected to the outputs of the variable and sum memory blocks, and the control input - with the corresponding output of the control unit, the first code converter, whose input is connected to the output of the variable memory block, two adders, information inputs the first of which is connected to the second information input of the variable memory block, the output of the communication unit with the computer and the output of the first code converter, the information inputs of the second one with the outputs of the incremental memory block and the first switch, and the control input of the second block of adders - with the corresponding output. control block, shift register block, the setup input of which is connected to the output of the first block of adders, control inputs, to the corresponding output of the control unit, and output to the second information input of the incremental memory block, four vector coordinate registers, whose information inputs are connected to the second information input of the sum memory block and the output of the second block of adders, and the control inputs with the corresponding outputs of the control block, and the second and third code converters, with the second input the code generator is connected to the input of the variable register along the X coordinate and the output of the first register of vector coordinates, and the output with the first input of the increment adder along the X coordinate, the second input of which is connected to the output of the third vector coordinate register and the input of the third code converter is the Y coordinate and the output of the second register of vector coordinates, and the output with the first input of the increment adder along the Y coordinate, the second input of which is connected to the output. fourth coordinate register of vectors. The control unit contains a clock pulse generator, the output of which is connected to the input of the frequency divider and the first inputs of the elements of the first group, the second inputs of which are the corresponding inputs of the block, the output of the frequency divider is connected to the first inputs of the elements of the second, third and fourth groups, the first input of the first counter pulses and the first input element And, the second input of which is connected to the second inputs of the corresponding elements And the second and third groups and one of the outputs of the register of control codes, the third input - to The first inputs of the fourth group elements and the output of the first decoder, and the output to the first inputs of the second pulse counter and the first OR element, the second input of which is connected to the input of the register of control codes and the output of the second OR element, and the output to the first input of the second switch, the second input of which is connected to the output of the register of the codes of the number of vectors, and the output to the second input of the first pulse counter, the output of which is connected to the input of the first decoder, the inputs of the second element OR are connected to the outputs of the elements AND the fourth the mouth of the group, the third inputs of which are connected to the second inputs of the corresponding elements of the second and third groups and the outputs of the register of control codes, the fourth input of one of the elements of the fourth group is connected to the output of the second decoder, the input of which is connected to the output of the second pulse counter, the second input of which connected to the output of the third switch, the inputs of which are connected to the outputs of the register of extrapolation codes and one of the elements of the fourth group, the outputs of the elements of the first group are connected to the third input m of the corresponding elements of the second and third groups, and the outputs of the corresponding elements of the second and third groups are connected to the inputs of the elements of the OR group, the output of one of which is connected to the input of the third pulse counter, the output of which is connected to the input of the third decoder, the output of which is connected to the fourth inputs elements And the third group.

FIG. 1 shows a block diagram of the device; in fig. 2 is an example of a time variation of one of the coordinates of a vector; in fig. 3 is an example of the input information; in fig. k - 6 - presentation of information, respectively, in the variable memory block, the increment memory block and the sum memory block; Fig. 7 is a functional block diagram of the control unit.

The device contains a block of 1 memory

variables, incremental memory block 2, sum memory block 3, control unit, address counter 5, computer communication unit 6, first code converter 7, first adder unit 8, block 9

shift registers, shift register 10, the first counter 11 shift pulses, the first switch 12, the second block 13 adders, the first register H of the coordinates of the vectors, the second register 15

coordinates of vectors, third register 1b coordinates of vectors, fourth register 17 coordinates of vectors, second converter 18 codes, third converter 19 codes, adder 20

increments along the X coordinate, adder 21 increments along the Y coordinate, variable register 22 along the X coordinate, variable register 23 along the Y coordinate, 2k increment register along the X coordinate, 25 increment register along the Y coordinate, scale register 26 along the Y coordinate, second counter 27 shift pulses, third counter 28 shift pulses, digital-analog

Converter 29 along the X coordinate, register 30 of the scale along the X coordinate, digital-to-analog converter 31 along the Y coordinate, the deflecting system 32 of the cathode ray tube (CRT),

33 clock pulses, frequency divider 3, the first group of elements And 35, the second group of elements And 36, the third group of elements And 37, the fourth group of elements And 38,

the first pulse counter 39, the AND kO element, the control code register, the first decoder 2, the second pulse counter, the first element. OR C, the second element OR, the second switch A6, the register of 47 codes of the number of vectors, the second decoder 8, the third switch 9, the register of 50 extrapolation codes, the group of elements OR 51, the third counter

52 pulses and the third decoder 53 The device operates as follows.

Claims (2)

Each image vector coming from a computer to be displayed on a CRT screen is represented as the coordinates of the beginning () and end (K, Y) of the vector.  The position of the vectors in space over time changes em-, p.  Let, for example, the coordinate X change with time according to FIG.  2  And the coordinates of Xj. X, Xfi Xj, X4 are output from the EVI, and intermediate coordinates marked with a double index are calculated in the device.  Coordinates are calculated using the formula CH X, the new value of the coordinate X, which comes from the computer, the previous value of the coordinate X, received by the computer.  KdH, K 0,1,2 ,. . . 2 (XH-Xc) -2p is an integer. (3) The value of p is selected depending on the speed of the computer, which determines the interval of outputting the image coordinates. The coordinates along the Y axis are calculated in the same way.  To display a CRT, the information should be presented in the form of S - bit numbers, where, in the general case, it does not coincide with the width of the input information.  Consequently, it is necessary to scale the variables 0Ь16 Х / х Yebie v / Ms ,, where Xgjj, g is the output value of the X coordinate: MX is the scale in X, Mx 2 n is an integer; Ygfjig is the displayed value of the Y coordinate; Mch; - scale by, Mu 2, k is an integer.  The operation of the device will be considered on the example of the representation of coordinates in the form of 1b-digit codes, each vector being output from the EMU as a sequence of four words (Fig.  3).  Further processing of coordinates occurs in tetrads m in a series-parallel way, starting with the lower bits.  In this connection, the first 1 second blocks 8 and 13 adders each contain four 4-digit adders, and the block 9 shift registers - four shift registers Before the device starts operation, registers 10, 30 and 26 should be initial 78 Pn; Go to fly accordingly.  Initially, the contents of the counter 5 address is 0.  The next word from the computer goes through block 6 to the first block 8 of adders.  At the same time, the corresponding word from block 1 of variable memory at the address determined by address counter 5, through the inverter 7 codes enters the second input of the first block 8 of adders and a constant from shift register 10 is entered into the first counter 11 of the shift pulses.  The first block 8 adders and block 9 shift registers implement the formula 3.  According to the signal from control unit 4, the contents of memory unit 6 are recorded into unit 1 of the variable memory, and the output of block 9 of shift registers is entered into unit 2 of the increment memory.  After that, the contents of the counter 5 of the address by a signal from the control unit is increased by 1 and, similarly, the next word from the computer is received.  Thus, blocks 1 and 2 of the memory of variables and increments are filled.  After the completion of the filling of blocks 1 and 2 of memory, the counter 5 is set to O. Through the first switch 12, the second block 13 of adders (without summation) the contents of block 1 is written into block 3 of the memory of sums.  In this way, the formulas (1) and (2) for K 0 are fulfilled.  In parallel with the output of the second block 13 adders, the word is written into the coordinate registers of the vectors.  Through the second and third converters 18 and 19 codes on increments adders 20 and 21 along the X and Y coordinates, increments are computed in X and Y, which are written to the highest bits of the registers and 25 increments in the X and Y coordinates.  At the same time, the higher bits of the registers 22 and 23 of the variables in the X and Y coordinates are written to the contents of the registers 14 and 15 of the coordinates of the vectors.  After that, the contents of the address 5 counter are increased by 1 and the next word is read from the variable memory block 1, the X and Y increments are calculated and the variables and their increments are written to the high bits of registers 22-25 with a simultaneous shift of these registers to the right by the tetrad .  The process is repeated four times.  After reading the four words in registers 22-25, 1b-tyrant words were formed.  In the second and third counters 27 and 28 of the shift pulses, the shift constants from the registers 30 and 26 of the scale are scaled by the coordinates X and Y and then the contents of the registers 22-25 are converted according to formulas () and (5): division by M is performed shift on n bits.  Codes from registers 22-25 are then converted to voltage in digital-to-analog converters 29 and 31, and through a deflecting system 32 CRTs are output to the EL screen. Next, the contents of counter 5 are incremented by 1 and the process is repeated.  When the memory of the sums is full (t. e.  in block 3 there is an initial value of the sum equal to Xj, the counter 5 of the address is set to O, the word from block 3 of the memory of sums through the first switch 12 is fed to the 2nd input of the second block 13 of adders, and to the first input of block 13 is fed the corresponding word from block 2 memory increments.  The second block 13 of adders implements formulas (1) and (2) with K 1.  In parallel with the output of the second block 13 adders, the word is written into the registers 14 of the 17 coordinate vectors.  Through the second and third converters 18 and 19 codes on increments adders 20 and 21, X and Y coordinates are incremented by X and Y, which are written to the high bits of registers 2 and 25, and to the high bits of registers 22 and 23 are written the contents of registers 1 and 15- After this, the contents of counter 5 of the address is increased by 1 and the next word is read from block 3 of the memory of sums, the increments are computed by X and Y and the variables and their increments are written to the high bits of registers 22-25- Simultaneously with this the contents of these shift registers ts to the right on the notebook.  After reading four words from block 3 of the memory of sums in registers 22-25, 1b-bit bit words were formed.  The counters 27 and 28 of the shift pulses enter the contents of the registers 30 and 26, and then the contents of the registers 22-25 are converted according to the formulas () and (3), and then the codes are converted to voltage in the digital-to-analog converters 29 and 31 through deflecting CRT system 32 is displayed on a CRT screen.  Further, the contents of counter 5 are incremented by 1 and the process is repeated.  After filling in block 3 of the memory of the sums, the values corresponding to (XH + 4X) are recorded in it.  Counter 5 of the address is set to O and the process is repeated for K 2,3 ,. . . , before the arrival of new information from the computer.  The operation of the control unit is as follows.  In the initial state, in the register of 7 codes of the number of vectors, the number of converted vectors is recorded, in the register of 50 extrapolation codes, the number K 2 is written, the value of the third counter is 52 pulses of the coordinate counter.  vector dinat) corresponds to 3.  We consider the operation of the control unit for the case when the initial value P 4 is set in the shift register 10, 2 is recorded in the scale register 26 on the Y coordinate, and recorded in the scale register 30 on the X coordinate (FIG.  one).  The generator 33 clock pulses forms a series of signals C1 with.  frequency f, and the output of the frequency divider C generates a series of signals C2 and with frequency t f in accordance with the value of P 4.  Bi operation of the control unit is allocated three states.  In the initial position in the control code register k, the first bit is set to 1, which determines the first operating state of the control unit.  According to C2 L C1, the corresponding elements And of the first and second groups 35 and 36 of the control unit, at the output of the block, a shift signal is produced, which is fed to the block 9 of the shift registers (Fig.  1), ensuring the implementation of the formula () 2.  By C2LC1, the same elements AND of the control unit at the other output of the block produce a signal that is fed to the first counter 11 of the shift pulses, and the contents of the counter are reduced by 1.  This operation will be repeated four times until the first counter 11 is set to 0.  Thus, formula (3) is realized.  According to C2, one of the elements AND ST of the second group and one of the elements OR 51 of the group at one of the outputs of the control unit generates an increase signal by 1 of the contents of the counter 5 of the address.  Then, in C2, another element of the same group generates a signal at the output of the block that writes to the block 1 the memory of the variable contents of the computer communication unit 6 and the block 2 of the memory increments of the block 9 of the shift registers.  C2, arriving at the counting input of the first counter of 39 pulses (the array dimension counter), reduces its content by 1.  The described process will continue until the array dimension counter is set to O, as indicated by the signal at the output of the first decoder 2.  This signal from the output of the control unit is fed to the counter 5 of the address, resetting it to 0.  By the same signal, one of the elements 38 of the fourth group and the second element OR 45 shift 1 in the control code register 41 to the second bit, the control unit transitions to the second state.  Parallel to the first elements OR 44, a signal is written to rewrite the contents of register 47 of the vector quantity codes through the second switch 46 to the counter 39 of mass dimension.  In the second state, the signal C2 at one of the outputs of the element management block AND and OR generates an increase signal by 1 content counter to 5 address, while the other outputs form signals arriving at the first switch 12 and the second block 13 of adders, allowing the passage data through the switch from the memory block of variables and prohibit the operation of summation on the second block of adders.  From the output of one of the elements of the OR 51 group, the pulse arrives from the third counter 52 (the vector’s coordinate counter), reducing its content by 1. According to C2, the corresponding AND and OR elements at the output of the control unit generate a write signal of the variable memory block into the memory block. ti sums  The same elements form a signal on during the control block, which, when registers 22 and 23 are variable along the X and Y coordinates, provides a shift by four bits in these registers and overwrites the contents of the registers 14 and 15 of the vectors coordinates registers 24 and 25 increments along the X coordinates and provides a shift of these registers 712 by four bits and recording of the calculated increments from the adders 20 and 21 increments along the X and Y coordinates; arriving at the registers 14-17 coordinates of vectors, gates the record from the second block 13 adders.  Four words are processed as described, and the vector coordinate counter 52 is set to 0.  According to C1L C1, the elements AND and OR of the block form the corresponding signals at the outputs of the control block. One of these signals on the variable register 22 along the X coordinate and the 24 increment register along the X coordinate is shifted by one bit.  Another signal on the variable register 23 along the Y coordinate and the 25 increment register along the Y coordinate is shifted by one bit.  For the remaining signals, the contents of the second and third counters 27 and 28 of the shift pulses, respectively, are reduced by 1.  This is repeated four times for the variable X and two times for the variable Y, t. e.  until the second and third shear pulse counters are set to 0.  The change in the state of the counter 39 of the array dimension occurs similarly to the description of the first state of operation of the control unit.  In C2, the corresponding shift elements for the register 41 of control codes 1 are shifted to the third register bit by the corresponding elements AND and OR, thereby establishing the third state of the control block.  By a signal from one of the elements of the OR 51 group, the contents of the register of 47 codes of the number of vectors are copied to the counter 39 of the dimension of the array.  At the same time, the signal from one of the elements 38 of the fourth group gates overwriting the contents of register 50 extrapolation codes through the third switch 49 to the second pulse counter 43 (extrapolation counter).  In the third state of the control unit, the signal C2 is formed at one of the outputs of the control unit. the signal increases by 1 the contents of the address counter 5, and on the other outputs, signals are received, respectively, to the first switch 12, allowing data to pass from the memory block of the sums and summing them with the data from the memory block of the increments on the second block 13 of adders.  From the output of one of the elements AND 36 of the second group, one of the elements of OR 51 of the group receives a signal at the counter of the 52 coordinates of the vector, reducing its content by 1.  The remaining signals at the outputs of the control unit are formed in the same way as in the second state of the control unit.  When in C2 the array dimension counter 39 becomes equal to O, the signal from the output of the element AND through the first element OR is overwritten from the holding register 7 codes of the number of vectors into the array dimension counter 39, as well as the contents of the second pulse counter — extrapolation counter 3 reduced by 1.  The whole process is repeated for the new K value.  When the extrapolation counter 43 is set to O, one of the fourth group AND 38 elements and the second OR 5 element produces a shift signal for the control code register 1 and 1 of the 3rd bit will shift to the 1st bit (cyclic shift), t. The control unit will enter the first state.  The technical effect of using the proposed device for displaying graphical information on a CRT screen is achieved by improving the accuracy of reproducing visual information about bodies moving at high speed and reducing the speed requirements of a computer, which prepares information for output to a device for display. Formula 1.  A device for displaying graphical information on a cathode ray tube (CRT) screen, containing a communication unit with a computer, a sum storage unit, the control input of which is connected to the corresponding output of the control unit, and digital-to-analogue converters in X and Y coordinates, the outputs of which are connected to the deflection system of the CRT, the inputs of the digital-to-analog converter on the X coordinate are connected to the outputs of the registers of the variable on the X coordinate and increments on the X coordinate, and the inputs of the digital-analog converter on the V coordinate correspond With the outputs of the variable increment registers along the H coordinate, the information inputs of the increment registers along the X and Y coordinates are connected to the outputs of the corresponding increment accumulators along the X and Yux coordinates of the variable registers along the X and Y coordinates — to the corresponding output of the control unit, which is , with the purpose of improving the accuracy of the device, it contains three shift pulse counters, the control of which inputs and outputs are connected to the corresponding outputs and inputs of the control unit, the shift register, the output of which is connected to the first input of the shift pulse counter, the scale registers along the X and Y coordinates, the outputs of which are connected to the setup inputs of the second and third shift pulse counters, respectively, the address counter whose input is connected to the corresponding output of the control unit, the variable and increment memory blocks that control the inputs of which are connected to the corresponding output of the control unit, and the first information inputs to the first information input of the memory of the sums and the output of the address counter, the first switch, the formation inputs of which are connected to the outputs of the memory blocks of variables and sums, and the control input with the corresponding output of the control unit, the first code converter, whose input is connected to the output of the variable memory block, two blocks of adders, the information inputs of the first of which are connected to the second information the input of the memory block of variables, the output of the communication block with the computer and the output of the first code converter, the information inputs of the second one with the outputs of the memory increment block and the first switch, and the control input second block of adders - with a corresponding output of the control unit, a block of shift registers, the setup input of which is connected to the output of the first block of adders, a control input - to the corresponding output of the control unit, and an output - to the second information input of the memory block of increments, four coordinate registers of vectors The information inputs of which are connected to the second information input of the memory block of the sums and the output of the second block of adders, and the control inputs to the corresponding outputs of the control block, and the second and third code converters, the input of the second code converter is connected to the input of the variable register along the X coordinate and the output of the first vector coordinate register, and the output with the first input of the increment adder along the X coordinate, the second input of which is connected to the output of the third vector coordinate register codes is connected to the input of the variable register by the V coordinate and the output of the second vector coordinate register, and the output is connected to the first input of the adder by the H coordinate, the second input of which is connected to the output do the fourth coordinate register of vectors.  2  The device according to claim.  1, so that the control unit contains a clock pulse generator, the output of which is connected to the input of the frequency divider and the first inputs of elements AND of the first group, the second inputs of which are the corresponding inputs of the unit, the output of the frequency divider is connected to the first inputs elements of the second, third and fourth groups, the first input of the first pulse counter and the first input of the element I, the second input of which is connected to the second inputs of the corresponding elements of the second and third groups and one of the outputs of the control register their codes, the third input - to the second inputs of the AND elements of the fourth group and the output of the first decoder, and the output to the first inputs of the second pulse counter and the first element OR, the second input of which is connected to the input of the register of up 716 716 equivalent codes and the output of the second element OR and the output is with the first input of the second switch, the second input of which is connected to the output of the register of codes of the number of vectors, and the output to the second input of the first pulse counter, the output of which is connected to the input of the first decoder, the inputs of the second element OR is connected s to the outputs of elements AND of the fourth group, the third inputs of which are connected to the second inputs of the corresponding elements AND of the second and third groups and the outputs of the register of control codes, the fourth input of one of the elements AND of the fourth group is connected to the output of the second decoder, the input of which is connected to the output of the second counter pulses, the second input of which is connected to the output of the third switch, the inputs of which are connected to the outputs of the register of extrapolation codes and one of the elements of the fourth group, the outputs of the elements of the first group We are connected to the third inputs of the corresponding elements of the second and third groups, and the outputs of the corresponding elements of the second and third groups are connected to the inputs of the elements of the OR group, the output of one of which is connected to the input of the third pulse counter, the output of which is connected to the input of the third decoder connected to the fourth inputs of the elements And the third group.  Sources of information taken into account during the examination 1. Newman U. , Sirull R.  Fundamentals of interactive computer graphics, M ,, World, p.  77-81, 1973.   2. USSR author's certificate №, cl. G About K 15/20, 1970 (prototype). SP 7С From computer five WITH //. i tj four n i / 3  f. I t / e I one five I 77 1y gt h: gr. Z2 I 3gl. I 27. 5 Zy M J X S X "y" XK y FIG. FIG. g 1st caoSo 2nd c / ioSo 3rd weak if-e c / ioSo FIG. five vH / H y and ..N ln jm l a yff