RU1807516C - Device for representing information on the cathode-ray tube screen - Google Patents

Abstract

SUMMARY OF THE INVENTION: the device comprises 2 switches, 5 registers. 1 shift register, 1 address counter, 3 buffer registers, 1 bus driver, 1 video driver, 1 shifter, 1 CRT, 1 synchronizer, 1 control unit, 1 address driver, 1 memory unit. 1 C.p. f-ls, 14 ill.

Description

The invention relates to automation and computer technology and can be used in display devices when it is required to move an image on a screen, convert video data in a mode specified by the processor, and exchange information with the processor.

The purpose of the invention is to increase the speed and scope of its application due to the possibility of representing the image in the windows of the screen by moving the image in any direction - programmable speed.

In FIG. 1 shows a structural diagram of a device; in FIG. 2 is a functional diagram of an address generator; in FIG. 3 is a timing diagram of the operation of the device, which shows the basic operations on the video data performed by the device in each cycle; in FIG. 4 - region of the coordinate space of the video memory: in FIG. 5 is a timing diagram of an operation of an indication mode device; in FIG. 6 shows possible page-by-page display options of video information; in FIG. 7a is a timing diagram of the operation of the device during the operation of reading words; in FIG. 76 - records in words; in FIG. j 8a - rolling up operation | h (down); on Fig, 86 - rolling left (right) j in the area of the screen; in FIG. 9 is a temporary C /) diagram of the operation of the device when f is rolling up (down); in Fig. 10-time diagram of the operation of the device 3 when performing the rolling operation to the left (to the right); in FIG. 11 - temporary; diagram of the operation of the device when performing the operation of bit recording; in FIG. 00 12 - functional diagram of the address decoder decoder; in FIG. 13 -function- xj is displaced shift register scheme; in FIG. (g 14 - shifter; l The device contains the first commutator. torus 1, register 2 of the starting address, the first 3 and second 4 registers of the current address (first and second pages of indication), the first 5 and second 6 registers of the modification address - (respectively, coordinates X and Y), counter 7: addresses, address shaper 8, first buffer register 9, memory block 10, shift register 11, second buffer register 12, bus shaper 13, second switch 14, third buffer register 15 , video former 16, cathode ray tube (CRT) 17, shifter 18, control unit 19 and no synchronizer 20.

The following positions are designated: 21 - input / output, 22 - input of the reset pulse, 23-input of the start pulse, 24-input of the end of interpolation signal, 25-28 - inputs of interpolation pulses + X, -X, + Y.-Y devices, 29-31 - communications of the respective blocks, 32 - information input of the device, 33-35 - communications of the respective blocks; 36 - the first information bus, 37-94 - communications of the respective blocks, 95 .- the second information bus of the device.

Shaper 8 addresses contains from first to third registers 96, 97 and 98 from first to third switches 99,100,101 and decoder 102 (address).

Registers 96-98 serve for temporary storage of generated address codes.

The infirmation input 36 is connected as follows: from the 8th to 15th, the bits are connected to the information input of the register 96, and from the 0th to 7th, the bits to the information input of the switch 99.

Information inputs 47 and 48 are connected as follows: from the 2–9th bit of the input 47, to the common bus and to the second information input of the switch 100, and from the 6–3th bit, with the information input of the register 98,

The decoder 102 consists of decoders 103 and 104 (two to four) and groups of elements 105-108 2I-NOT, 0 and 1, 3, and 4 bits of the address bus (output 61) determines the signal selection RA and CA respectively, in bit recording mode.

The shift register 11 consists of shift registers 109 and 110, which makes it possible to sequentially shift 16 bits of the video word word1 recorded in the form of a parallel code in the register 110 during the device operation period.

The shifter 18 consists of a shift register 111 and a switch 112.

The control unit 19 can be synthesized in various ways and presented in the form of time diagrams fully reflecting all the control signals generated by the unit.

For the sake of definiteness, the description of the operation of the device will be performed for 16-bit address operands and 16-bit video layers, which determines the bit sizes of the function blocks and information buses of the device in the description below.

Switch 1 provides information to output 29 from one of its information inputs, one of which is connected to input / output 30 and the other to input / output 21 of the device, which is used to receive data from the processor (not shown in the drawing).

Register 2 of the real address is used to set the initial address of the 1st or 2nd display page. The lower 15 bits of the information input 32 are connected to the logic zero output, and the weight of the senior 16th bit sets the address of the 1st or 2nd page.

Output 35 is connected to data bus 36.

Registers 3 and 4 are registers of the current address of the 1st and 2nd display page, respectively, and serve to store the current addresses of the 1st and 2nd display page, respectively (addresses of the 1st and 2nd page of the video memory )

The outputs 41 and 42 of the registers are connected to the information bus 36.

Registers 5 of the address (X) and register 6 of the address (Y) of the modification serve for storing 16 bit addresses recorded in these registers from the processor or from input 30.

The output 47 of register 5 is connected as follows: 16 bits with a bus 36, and 10 low-order bits with the information input of the shaper 8. The output 48 of register 6 is connected: 16 bits with a bus 36, and 10- ten younger ones - with the information input of the shaper 8.

Registers 2,3,4,5 are registers with a third state, because information outputs of these registers are connected to the same 16-bit information. a bus 36, which is also connected to the information input of the counter 7. and a 16-bit input of the driver.

Counter 7 addresses are intended:

1) to increase the current addresses of the 1st or 2nd display pages, stored respectively in registers 3 and 4, as well as in register 2;

2) to change the modification address stored in registers 5 and 6 by decrement or increment, depending on the operating mode of the device.

The address generator 8 serves to generate the address operands of the memory unit 10 and the corresponding signals of the memory matrix samples.

A buffer register 9 serves for temporary storage of data.

The memory unit 10 serves for operative storage of video data, with their subsequent display on a CRT at the corresponding addresses.

Block 10 is a dynamic type RAM and is a 4x4 chip array spanning a memory area of 1024x1024 bits.

The 8-bit input of the chip selection serves to receive the sampling codes from the output 61 of the driver 8, and contains the 4th bit of the RA signal (row selection signals) and the 4th bit of the CA signal (column selection signals). Using these signals, a chip is selected memory matrix for addressing, writing, or reading video data.

Shift register 1.1 is used to convert the parallel code of video data to serial.

Buffer register 12 serves for temporary storage of video data read from block 10.

The bus driver 13 serves to output data from the register 12 to the information highway 21, as well as to transfer the output 72 to the high impedance state when data is being written from the processor to the register 15.

The buffer register 15 is used to temporarily store a code of video data recorded from the processor.

Video shaper 16 is used to convert a serial digital code of video data into analog signals, followed by a CRT display.

The shifter 18 serves to:

1) storing and transmitting information read from the switch 14 and from the information input 78, bit data;

2) to shift data words by one bit in horizontal rolling mode.

The control unit 19 serves to select control signals, depending on the operating mode of the device.

The information input / output of the block is connected to the information highway 21 and is used to receive control codes from the processor, by which the internal ports of the block are programmed for the corresponding mode, and also to issue control codes to the processor for monitoring the operation of the control block.

The pulse synchronizer 20 is designed to select the TO-T4 clock frequencies, respectively, according to the first and second outputs 90-94, necessary for the temporary synchronization of the block

The device operates as follows:

zom.

The period of operation of the device (the period of the frequency T2 formed at the output 94 is covered) can conditionally be divided into four clock cycles (see Fig. 3). For a given period of time

The device can work out two modes:

1. Indication mode.

2. Modification mode.

The display mode is intended for reading video data from block 10 at specified addresses for subsequent display on CRT 17.

The modification mode is intended for reading video data from block 10 and for their further conversion, as well as for recording video data in block 10 from a processor or from an interpolator at specified modification addresses.

For the indication mode in the 1st and 2nd cycles), data is read from block 10 and the next address for reading is prepared, and in the 3rd and 4th cycles the read data is displayed on the CRT, and also continues to be displayed on 1- m and 2 bars of the following periods, in which it in turn prepares: again the next address to read.

In the modification mode, in the 3rd and 4th clock cycles, a modification address is generated at block 10, at which writing (reading) to (from) block 10 is performed, and the next modification address is prepared for reading (writing) to (from) block 10. A in the 1st and 2nd cycles, the modification mode is not performed, but only the information is read from block 10 and indicated on the CRT. For each period of operation of the device, two modes can be worked out.

Depending on the mode of operation, it is possible to display and convert information both bitwise and in words of video data. The area of the memory block has a dimension of 1024x1024 pixels: 1024 columns and 1024 rows (see Fig. 4). Each line has 1024 points, i.e. 210. Each word contains 16 dots, i.e. 24. Each line contains 64 words, i.e. 36. To convert the information in bits, a 20-bit point address is used: 10 bits in the X coordinate (rows) and 10 bits in the Y coordinate (columns). To convert information into words of video data, a 16-bit address of the word is used, in which 6 bits cover the columns and 10 bits cover the rows.

The presentation and transformation of information using words is used in the case where high speed is required to move a large amount of information in the memory area. Information processing is applied bit by bit in the case where the conversion and display of information with a resolution of up to one pixel is required.

In this device, the area of the block 10 of 1024x1024 pixels is divided into two display pages, in particular: 1- a page with a size of 1024x512, 2- a page with a size also of 1024x512 (vertical split). There is a possibility of horizontal partitioning of the video memory area. The partition boundary, in this case, is set by the processor using the boundary addresses.

The frequencies TO, T1, T2, TK, CLK, which are formed respectively at the outputs 90.91.92.93.94 of the synchronizer 20, synchronize the operation of block 19.

Before starting operation of the device, the processor at the input 22 generates a reset signal, through which the internal ports of the control unit 19 are reset.

Consider the operation of the device in display mode.

A timing diagram of the operation of the device in this mode is shown in FIG. 5. In the first measure (, T2 0), the counter for address 7 of the address of the 1st page is recorded (the initial moment from register 2 or currently from register 3), as well as its incrementation to counter 7 and the address of the first page is written to the shaper 8 addresses. After that, the address of the 2nd page is set on the bus 36. In this case, the following micro operations are performed. At the beginning of the forward stroke of the frame, low levels are set at the inputs 33.34 of register 2, as a result of which the data (starting address of the 1st display page) from register 2 is received from its output 35 to bus 36. At the input 49, write permissions to counter 7 a high active level is also set on the trailing edge of the pulse from the output 94 of the CLK frequency supplied to the clock input of the counter 7. Data from the bus 36 is written to the counter. At the time of writing to counter 7, the same data will be recorded from bus 36 to the registers 97 of the shaper 8. Moreover, 8 high-order bits of the address are written to the register 96, and a low-order bits 97 to the register 97. Writing to the registers 96 and 97 is performed by the leading edge of the signal 52 and the leading edge of the signal 56, respectively. At this time, at the control inputs 53 and 55 of the switches, the 99 and 101 levels are logical units. Therefore, the low byte of the address is generated at the output 60 of register 97 and written to the internal registers of block 10 according to the RAS signal, which is generated in this cycle at the output 61 of the decoder 102. By the RAS signal in the matrix of block 10, microcircuits are selected in rows, the internal registers of which are written low byte of the address. Then, at the input 49 of the counter 7, the active recording level is removed, single levels are set at the inputs 50 of the resolution of the account and 51 of the direction of the account, and the rear

the front of the signal 94 With K there is an increase in the contents of the counter 7 per unit. For decoder 102, signal 57 is set to O level to enable all RAS and CAS signals of all memory chips,

0 and signals 58 and 59 define the pulse shape of the RAS and CAS signals, respectively,

After recording the first display page, a high signal level 24 is set, as a result of which the output 35 of register 2

5 sets the start address of the 2nd page.

In the second step (,), the incremented address of the 1st page is rewritten from counter 7 into buffer register 9 and is entered into register 3 of the current address of the 1st page. At the beginning of this measure, the address of the 2nd page is written to counter 7 (at the initial moment from register 2 or at the current moment from register 5), as well as its increment to counter 7. In the same measure, at the output 60 of the former 8 set the high 8th bits of the 1st page address are stored, which were stored in register 96, and are formed

0 CA signals on bus 61.

In this case, the following micro operations are performed.

The leading edge of a single pulse of the signal 62 is written to the register

5 9, the data output of which via bus 30 goes to the information input of register 3 and is written into it by a zero signal level 37. At the input 49 of the recording enable counter 7 is formed active

0 unit level. On the trailing edge of a single pulse of the 94 CLK signal, data is written to counter 7. Since at the inputs 50 and 51 are unit levels, then the next signal CLK increments the information recorded in the counter 7. A zero level is formed at the control input 53 of the switch 99, and a single level is supported at the control input 53 of the switch 101. Hence,

0, the high byte of the 1st page address from register 96 is received at the information input of register 97 and the leading edge of a single pulse of signal 56 is recorded in register: 97 and set at output 60.

5 The specified address byte is written to the internal registers of block 10 by CAS signals. Based on the CAS signals in the matrix of block 10, microchips arranged in columns are selected in the internal registers of which the high byte of the address is written. Thus, in the internal registers of block 10, a 16-bit address of the 1st page is recorded. at the moment of coincidence of the RAS and CAS signals to the zero state, this address (in this case) is recorded in all microcircuits of the matrix of block 10.

Since a single level is formed at control input 63 in this mode, the video data word at the specified address is generated at the output 65 of block 10.

In the third measure (,), the incremented address of the 2nd page is rewritten in register 9 and entered in register 4 of the current address of the 2nd page. At the beginning of this clock, the word of the 1st page of video data from the output 65 of block 10 is written into the shift register 11, converted from parallel to serial code in it, fed to shaper 16 and started to be displayed on CRT 17.

In this case, the following micro operations are performed.

The rewriting of the incremented address of the 2nd page to register 9 and then to register 4 is done; accordingly, the leading edge of the signal 62 and the zero level of the signal 38. Record in the register 11 is carried out by the leading edge of the signal 65. The signal C To shift the recorded information, transfer to the output 67 and enter in the former 16, where they are converted into the form necessary for display on a CRT.

In the fourth clock cycle (,), the next address of the 1st page from register 3 is set to bus 36. The following micro operations are performed.

At the input 39, a low level signal is supplied to register 3, as a result of which, the data recorded in it in the 2nd cycle are exposed on the bus 36 and begin to be written to the counter 7.

The video data read at the end of the 2nd measure will end up being displayed at the end of the 2nd measure of the next period by the moment when it is ready to display the data read at the next address.

The above indication mode procedure refers to the case where the first page is displayed on the CRT and then the second page (see FIG. Ba. B). To display the 2nd page on a CRT (see FIG. BB), similar operations are performed, with the difference that the operations performed on the 1st page address are changed to the operations performed on the 2nd page address, and vice versa. Those. in the first step,) the address of the 2nd page is recorded in the page counter 7 and in the shaper 8. And in the second measure

(,) the counter of the 1st page, etc. is written in the counter 7.

In the case where the 1-page is indicated on the CRT screen, the current address of the 2nd 5th page is prepared but not displayed, and vice versa.

In the display mode, it is also possible to display fragments of two pages on a CRT at the same time. This allows you to create windows on the screen, each of which displays its own information. Splitting into two windows can be performed both vertically and horizontally (see Fig. 6 c) and is set by the processor using the address of the border. In the case of vertical partitioning into two windows (see Fig. 6c), each line first displays, for example, 25 words of the first page, then p. On the 20th word, the indication of the 2nd page begins according to the above procedure., This is done by comparing in block 19 the current address on bus 30 with the address of the processor on bus 21. Then, on a new line, the processor returns the indication of the 1st page and so on. .d.

In the case of horizontal partitioning into two windows (see fig. Bg), for example, 250 lines of the 1st page are displayed, and starting from 251, 250 lines of the 2nd are displayed

0 pages.

Horizontal pressure can be set in increments of one line. Border addresses are located on the line relative to which pressure

5 on two windows.

In data modification mode, one of the following operations may be performed: 1. Reading in words. .

0 2. Record in words.

3. Bit reading.

4. The record is bit.

 5. Relocation of information on the screen. Consider a read operation in words in modification mode 5. A timing diagram of performing a word reading operation is shown in FIG. 7a. A word read operation is intended for reading 16-bit data from memory to a processor.

Consider the device performing this operation.

The initial cycle in this case will be the third cycle (,) of the operation period 5 of the device. The address of the data word (address X), previously prepared in register 5 and set on bus 36 in the 2nd cycle, is written to counter 7 and to shaper 8. Then, in the 3rd cycle 3, address Y is set similarly from register 6 to bus 36 - When

In a complex reading, address X is the address at which data will be read from block 10 to the processor, and address Y is not informative in this operation. In the same cycle, the control unit 19 analyzes the status of the inputs 25 (+ X), 26 (-X):

00 - prohibited state;

01 - incremental address X to the counter 7;

10 - decrypting address X to counter 7;

11 - prohibition of the account.

Depending on the above analysis, corresponding signals are input to the account resolution input 50 and the count direction input 51, at which microoperation is performed on the address X recorded in the counter.

Consider which microoperations are performed in step 3.

The write signals to the counter 7 and the shaper 8 are generated in the same way as in the display mode. Addresses X and Y are sent to bus 36 from register 5 and 6 by a low signal level 31 and 33, respectively. Increment or decrement of the address X recorded in counter 7 occurs along the trailing edge of the next signal 94 C K.

In the fourth cycle, address X is rewritten from counter 7 to register 9 and then from register 9 through switch 1 to register 5. In the same cycle, address Y from bus 36 is written to counter 7. In the fourth cycle, the processor has access to registers 5 and 6, in the case of setting the read address. When the processor accesses registers 5 and 6, switch 1 switches to data from the processor. Also, in this case, also the formation of the outputs 60 and 61 of the driver 8 of the address X of the data word and the chip selection code, respectively. In this case, the following micro operations are performed.

The write to the register 5 is carried out by the zero level of the signal 43. The microoperation of the write to the counter 7 of the address Y is carried out by the high level of the signal 43. Since at the output of resolution 50, the count in this clock cycle is low, then no operations on address Y are performed. Formation at the outputs 60 and 61 of the shaper 8 of the address X of the data word and the chip selection code occurs as well as in. indication mode. A start signal 23 is generated at the beginning of the fourth clock cycle. This signal reads from the memory the word of the video data at address X and the subsequent microoperations of writing (reading) to / from the block

10 until the processor removes the specified signal.

In the first clock cycle (,), a constant address Y is written from counter 7

to register 8 and then through switch 1 to register 6.

At the same time, the data at address X from the output 65 of block 10 is overwritten into the buffer register 12, and, if necessary,

0 through bus driver 13 via bus 72 are fed to line 21 and are read to the processor. Thus, reading a data word occurs in two stages. The processor first writes the address

5 to register 5, and then reads data from register 12. If you need to read data from neighboring addresses, you need to set the signals 25 (+ X) or 26 (2X) to a low level and then with each reading

0 from register 12 of the video data word, the address recorded in register 5 is automatically increased or decreased at the moment when it is in counter 7.

5 Writing to the register 6 is performed by a low-level signal at the input 44. Writing to the register 12 of the read word from block 1 is carried out by the leading edge of the signal 68. When the processor reads the data word on

0, control input 73 of driver 13 is set low and data from output 72 begins to be read to line 21.

In the second cycle from register 5 to bus 36

5, the next address X is set, and if at that moment there was no clock cycle for reading data from register 12, then this address passes through counter 7 without change.

Consider a write operation with words.

0 A word write operation is intended to write data words from the processor to block 10. A timing diagram of this operation is shown in FIG. 76. In the 3rd and 4th cycle () the formation of addresses (in

In this case, the address of the record in the memory of the word) occurs in the same way as the formation of the addresses during the read operation by words. In the 3rd cycle, at input 77, a low-level signal is written to buffer register 15

0, the processor data word and through the switch 14 is transferred to the information input 76 of the shifter 18. When this operation is performed, the shifter 18 operates in the mode of parallel recording of information, therefore, code 11 is generated at the outputs 79, 80 of the shift direction (there is no shift), at the output 81 switching information inputs 76 or 78 and a single level, i.e. switching of input 76. In the same cycle, at the input 82, the leading edge of the pulse sequence of the write signal records information into the shifter 18 from input 76 and transfers it over the fourth cycle to bus 64. In the first cycle, data is written from bus 64 to block 10.

It should be noted that, as with the read operation, there is the possibility of changing addresses using the signals at inputs 25 (+ X) and 26 (-X).

Consider the operation of moving information on a screen.

This operation includes the following varieties:

1. Rolling up or down.

2. Rolling left or right.

3. Moving information in any direction.

When rolling up, the device works in general as follows.

An external device via bus 21 programs the internal ports of the control unit 10 for rolling up operation. At the same time, the shifter 18 is set to parallel recording mode, the switch 14 is opened to pass data from the register 12. The processor writes to the register 5 the address X, from which the video data word will be read from the memory, moreover, at the time when, on the bus 30 address X must be located previously in register 5. Then, similarly, address Y is written in register 6, i.e. the address at which the video data word is read in block 10, read out at address X. A start signal 23 is generated at a point in time,. This signal reads from the memory of the word at the address recorded in the register 5 and formed accordingly by the shaper 8. The read information through the switch 14 is written to the shifter 18, and fed to the information input of the block 10 and written to the address recorded in the register 4 and formed accordingly by the shaper 8. At the same time, with the arrival of addresses X and Y on the shaper 8, they also go on the bus 36 to the counter 7 and increase by one for each recording cycle. And when rolling down, the current containing registers 5 and 6 decrease.

Thus, the addresses of words in a string are sequentially rewritten to new addresses so that the familiarity of the rewritable layer is shifted strictly in vertical position up or down a string. Therefore, the discreteness between addresses X and Y is 64th. In FIG. Figure 8a shows a rolling up or down rolling procedure.

It is possible to rewrite the word addresses in the vertical direction and across several lines (as determined by the addresses themselves). The smoothness of the movement of information depends on this 5. The more consistent the rewriting, the smoother the movement of information and vice versa. Obviously, the discreteness of address rewriting can be used to set the speed 0 of information movement.

The rolling up (down) operation includes the following micro operations.

Timing diagram of a device performing an up (down) rolling operation

5 is shown in FIG. 9. For convenience of description, we divide the TK frequency period into 8 clock cycles and the formation of control signals in the future will be considered relative to the indicated clock sequence. The start signal 23 comes at the beginning of the 2nd measure. In the 2nd step, data appears on the bus 36 read from register 3 and at the beginning of the 3rd step are written to the counter 7 and to the shaper 8. In the 3rd step, the address written to the counter 7 is incremented. In the 4th cycle, the changed data appears on the bus 30 and is again written to register 3. In the 3rd cycle, the contents of register 4 appear (the current address of the 2nd

0 si), in the 4th cycle they are recorded in the counter 7, incremented and in the 5th cycle are recorded in the register 4.

Those. microoperations of the indication mode were processed. In the 4th step on the bus 36

5, the contents of register 5 appear (the address X written from the processor) and at the beginning of the 5th clock cycle are written to the counter 7 and the shaper 8 and without changes in the 6th cycle, through the switch 1 is written to the register

0. 5. And from the shaper 8 in the 5th and 6th clocks, the address is sent to block 10, and video data is read from it from block 10. At the beginning of the 7th cycle, the data read in block 10 is written to the register 12 and then through the switch 14 they are fed to the information input of parallel data of the shifter 18. At the beginning of the 8th cycle by the signal 82, the data received on the shifter 18 are written to it and transmitted by

0 bus 64 to the second information input of block 10. In the 5th cycle of the same period of the frequency of the TK on the bus 36 appears the contents of register 6 (address written from the processor address Y). At the beginning of the 6th cycle, the address is written to counter 7 and unchanged through register 9 and the switch 1 is written to register 6. From the beginning of the 7th cycle, the same operations occur as in the 2nd and 3rd cycles for registers 3 and 4, i.e. current addresses are read for indication. In the 8th measure

on 1 36 the contents of reg-5 are read and fed to counter 7 and the shaper

page 6 and at the beginning of the first measure of the next p; 8. At the beginning of the 5th measure, the address X is recorded

TK rides are recorded in counter 7 and counter 7 and the corresponding driver 8 is formed. In general, the outputs 60 and 61 are formed. Next, the contents of counter 7 are increment 5 of the clock 8. In the 6th cycle, address X is unchanged

is changing. In the 2nd step of the next, it reads from the counter 7 and, passing through

TK on the bus 22 appears register 9 and switch 1 is recorded

the contents of the counter 7 and is written yelling into register 5. In the 5th clock cycle 36

register 6. And with the shaper 8, the contents of register 6 are counted (the address

of register 6, address Y goes to block 10 and 10 U) and at the beginning of the 6th beat is written to the count, this address is recorded at 7 and then in the 7th beat without changing

block 10 of the data set on its second-through register 9 and switch 1 is written in the information input 64.c to register 6. In the 5th, 6th, 7th clocks, indices in the clock cycle of the next period of TK are read from block 10

36, data is read from register 5, on-15 video data in the 3rd and 4th clock cycles. At the beginning

After the 2nd cycle, the specified data of the 7th cycle is the address X is written to the register

are incremented in counter 7, willow 3-m12 are incremented. Thus, in register 12 is

a cycle through the switch 1 is recorded as a video; read from block 10

register 5. That is, the next hell is prepared, in measures 5 and 6 at address X from the register

read for reading. And so on, until 20 5, and in shifter 18 - the word video data,

stop at a given address X or Y counted from block 10 in the 1st and 2nd cycles at

the processor. Microoperations when rolling address Y from register 6 to the start signal and

downwards are performed in a similar manner, with an entry in shifter 18 at the beginning of the 4th

the difference is that a clock cycle is performed on counter 7. In the 7th and 8th clocks from block 10, read data decrypting. It should also be from -25 views for the indication, which is to note that when rolling up the contents will be displayed in 1,2,3,4-th clock cycles

Register 5 is larger than the contents of Register 6 in the above procedure. The value is young with a resolution of 64, and when rolling the lower bit of the information output, 69

- on the contrary. the register 12 goes to serial

Consider how the left shift input 70 of the shifter 18 performs the operation 30, and the left roll (left). Temporal dependence of the senior level of information

the ability of the device to work when the output 69 of the register 12 arrives at the subsequent operation is shown in FIG. 10, optional input 71 of shifting to the right by shifter, temporary distribution of signals of bodies 18. When shifting to the left by control

43-46.68 is the same as on the temporary zav-35 inputs 79 and 80 (direction of shift) code

of the ropling operation upside down (down). combination 01. At the input of switching 81

When rolling to the right (left), it carries out the value of a logical unit, due to

with sequential read from the block, serial

XUaddress in each line of words and re-entry shift left 70. At the beginning of the 8th measure on

recording them in block 10 at address Y such 40 leading edge of the signal 82 occurs

so that the information is shifted by the shift of the contents of the shifter 18. Moreover,

line left or right by one discrete. the value of the least significant bit 70 takes

Usually, when you shift left, the address Y is at the same place as the high-order bit of the content. The bit is less than the address X and vice versa has pinned 18, and the least significant bit

right shift. The processor writes to re-45 of the shifter 18 during the shift process is lost. AT

histr 5 on bus 21 through the switch the address is the same clock shifted. the data arrives

X at the time when block 10 is located on bus 30. Also in the 8th cycle from register 6 to

address X, previously located in region 36, is read address Y and at the beginning of the 1st

page 5. Then, similarly, in register 6, the clock is written to counter 7 and the address U is formed. Before 50, 8 appears, the start signal is incremented and rewritten to block 10, it is contained in register 6. In the 1st cycle, the bus 36 sec

press register 6, but writing to block 10 of register 15 reads the address X and therefore does not happen to the address. At counter 7, it is dogically incremented and rewritten to

start signal no operations on the data-register 5. Next, the shaper 8 addresses with

mi is not executed. At the beginning of the 2nd step, the ne-55 of register 6 will go to the block at 10 and in the 1st and 2nd

the frequency frequency of the TK (,), the steps are formed, the content is recorded

signal 23 start. In the 2nd and 3rd cycles, the execution-shifter 18 (shifted data). Further in

similar micro operations are performed as on the fourth measure along the course of 76

when rolling up / down). In the 4th step of the register 12 in the shifter 18,

bus 36 reads the contents of the register processing in a given clock in parallel recording mode, video data at address X (incremented) is written to register 12 from block 10, which, in turn, is incremented again. is written to register 5, etc. on a cycle to a stop set by the processor. A glimpse of performing the rolling operation to the left (right) is shown in FIG. 86.

When rolling to the right, similar microoperations are performed, with the difference that the contents of the address Y are greater than the unit of address X. The value of the high order of the output of register 69 of register 12 is written to the sequential input 71 of the shift to the right of the least significant bit of the contents of the shifter 18, and counter 7 produces adding to the addresses arriving at it. At the same time, at the inputs of the direction of shift 79 and 80, code 10.

It should be noted that the device can move information from any angle. This operation is performed similarly to the up (down) rolling operation, with the difference that the address of the word being read is rewritten to the address located not in the vertical direction (as when rolling up (down)), but at the required angle, which is determined by the processor.

Consider the operation of reading household. This operation is as follows. The processor sets the address at which the word containing the data bit to read is read from the TO unit. Moreover, the operation of reading the specified word completely repeats the operation of reading words described in the above description. Then, the read word is processed by the processor, i.e. the required data bit is in the read word.

Consider the operation of writing bit. The operation is intended to record in block 10 one bit of video data. The time dependence of this operation is shown in FIG. 11. Bit recording has two varieties: recording from the processor and recording from the interpolator. Recording from the processor is as follows.

The processor on bus 21 enters the address of the recorded point in register 5 and 6: in register 5 - the address in coordinate X, and in register 6 - the address in coordinate Y, which completely determines the location of the recorded point in the coordinate region. Moreover, loading in registers 5 and 6 is performed in the same way as in the rolling operation. A temporary dependence of work

When performing the bit recording operation, the device obeys the time dependence of the data modification mode.

A value of logical 1 is generated in the bit record at input 57, as a result of which a chip selection code is generated at the output of decoder 102, depending on the code coming from the output of register 97, from which one 0 of the 16 chips of the matrix of block 10 is selected. In this case, the following micro operations are performed. Logic O value is supplied to input 55 of shaper 8, therefore, information inputs 5 47, 48 are initialized and the recording address is generated by the following chain: switch 100-switch 101 - register 97 - output 60, and generation of the chip selection code of the matrix of block 10 by chain: register 98-de0 encoder 102 - output 62. In the 3rd step of the frequency period T2, the address X is written in block 10, followed by the RAS signal code at output 61. Therefore, its second information input 5 is switched on switch 100 (4-9 bits of the address X and 0-1 bits of the address CA Y), the contents of which are transmitted in a chain: switch 100-switch 101-register 97-output 60 to output 60. The signal is selected RAS

0 row of the block matrix of 10 m the contents of output 60 are entered into the internal registers of the microcircuits selected in the row. Then, at the output 60, the contents of the first information input of the switch are formed

5 100 (2-9th bits of the address Y). The code in the CAS signal selects the rows in the matrix of block 10 and the newly generated content is written to the output 60 in the internal registers of the circuits, the output is 60. At the crosshairs

0. of the selected row and column of the matrix of block 10, there is that microchip of block 10 into which the bit address is written, because it will coincide in the zero state of the RAS and CAS signals, namely, one of

5 4-bit RA signals and one of 4 CAS bits in the 8-bit sample code will take the zero state.

Obviously, in the above-described modes, a logical O value is generated at input 57, as a result of which all RAS and CAS signals take a zero value and all microcircuits of block 10 are selected. A logical O value is set at input 81, as a result of which on the shifter 18

5, a data bit trip 78 is switched. The video bit recorded by the processor on the bus 21 to the internal register of block 19 is read to the input 78 of the shifter 18 and appears on all bits of the bus 64 and is fed to the second information input of the block 10. Upon the arrival of the start signal 23, the block 10 set by the address on the bus 60 of the driver 8 of the content of the second input of the block 10 to the selected chip. To record the next point, the processor similarly writes the new address of the point. The start signal is charged only at the time of recording one point from the processor, after which it is taken according to the device’s timing diagram, a single signal level 53 indicates that addresses for reading indication mode data are generated in block 10, and the signal level 53 is the address from switch 100. for example, in bit recording mode (see figure 11).

The bit recording from the interpolator is performed as follows.

The loading of registers 5 and 6, the formation of addresses and samples on the shaper 8 occurs in the same way as in the bit record from the processor. The difference lies in the fact that the formation of successive addresses (increase or decrease) occurs using the values of incremental increments at the inputs 25 (+ X). 2b (-X), 27 (+ Y), 28 (2Y), which are the outputs of the interpolator. Code combination of signals 25, 26 for address X or 27, 28 - for address Y set the counter mode of counter 7:

00 - prohibited state;

01 - incrementing the address X or Y;

10 - decrementing the address X or Y;

11 - prohibition of the account.

When data from register 5 is on bus 36, the value of inputs 25 (+ X), 26 (-X) is taken into account, and when data from register 6, the values of inputs 27 (+ Y), 28 (-Y) are taken into account. Recording and changing addresses, in this case, will occur on a signal 23 start. The video bit will be recorded in the same way as the above operation. At 24, the start signal is removed at the end of the interpolation. Therefore, writing to block 10 and address change at the counter 7 is stopped. -.

In the proposed device, information processing can be performed both bitwise and word by word, which significantly improves the productivity and flexibility of the device. Productivity of the device is achieved due to the fact that the movement of large amounts of information on the screen is performed by reading immediately the target word of the video data and writing it to the moving address (e.g., vertical rolling). Moreover, the speed of movement is set using discreteness of addresses, taking into account the smoothness of the movement of information.

Claims (2)

In the proposed device, the video memory area is divided by address method into two independent pages, which allows two windows to be formed on the screen, in each of which its video information is displayed and processed. SUMMARY OF THE INVENTION 1. A device for displaying information on a cathode ray tube (CRT) screen, comprising a start address register, an address counter, a memory unit, a shift register, a control unit, a video signal conditioner, the output of which is connected to the CRT modulator, and a synchronizer. the first output of which is connected to the first clock input of the control unit and the shift register clock, the recording enable input of which is connected to the first output of the control unit, the second output of which is connected to the control input of the memory unit and, the output of which is connected to the information input of the shift register, the output of which is connected to the information input of the video signal shaper, the information input of the start address register is the information input of the device, the output of the start address register is connected to the information input of the address counter via the information bus, control input recording which is connected to the third output of the control unit, the counting input - with the fourth output of the control unit, characterized in that, in order to increase the speed and devices and expanding the scope of its application due to the possibility of presenting the image in the screen windows by moving the image in any direction, programmable at a speed, it contains the first and second registers of the current address, the first and second registers of the modification address, the address generator, the first, second and third buffer registers, first and second switches, bus driver and shifter, the output of which is connected to the information input of the memory unit, the address input and the sample input of which are connected , respectively, with the first and second outputs of the address generator, the first information input of the first switch and the information input of the third buffer register are connected to the second information bus, which is the input-output of the device and to which the output of the bus driver is connected, the control input of which is connected to the output of the control unit, and the information input with the output of the second buffer register connected to the first information input of the second switch, the second information input of which is single with the output of the third buffer register, the control input of which is connected to the sixth output of the control unit, the seventh output of which is connected to the control input of the second buffer register, the information input of which is connected to the output of the memory unit, the eighth output of the control unit is connected to the control input of the second a switch, the output of which is connected to the first information input of the shifter, the inputs of left and right shift control of which are connected respectively to the outputs of the lowest and highest bits of the second buffer register, the second information input of the shifter is connected to the ninth output of the control unit, the tenth and eleventh outputs of which are connected respectively to the first and second inputs of the direction of shift of the shifter, and the twelfth and thirteenth outputs are connected to the inputs of switching and recording control of the shifter, respectively, the fourteenth output of the block control is connected to the control input of the first switch, the second. the information input of which is connected to the output of the first buffer register and the information inputs of the first first and second current address register and control unit, control inputs connected to address shaper fifteen of the twenty-second outputs of the control unit, outputs of first and second address registers modifications connected respectively to the first and second information input of the address and data bus through the first - to the information input of the address counter, the output of which is connected to the information input of the first buffer register, the outputs of the first and second registers of the current address are connected through the first information bus to the third information input of the address generator, the outputs of the first and second registers of the current address are connected to the information bus through the first information bus at the input of the address counter, the output of the first switch is connected to the information inputs of the first and second, respectively Modification address registers, recording control inputs and data output enable inputs of which the start address register and current address registers are connected respectively to the twenty-third through thirty-second outputs of the control unit, the input-output of which is connected to the second information bus, the second to fifth clock inputs control units are connected respectively to the second and fifth outputs of the synchronizer; from the first to seventh control inputs of the control unit are respectively the reset pulse input, the input start pulse, input signal of the end of interpolation + X, - X, + Y, -Y of the device, the first output of the synchronizer is connected to the control input of the video signal conditioner and the clock of the address counter, the thirty-third and thirty-fourth outputs of the control unit are connected respectively to the input the direction of the net address counter; and the write control input of the first buffer register. 2. Device pop 1, characterized in that the address generator comprises first, second and third registers, first, second and third switches and a decoder, the control inputs of which are the control inputs of the driver, the first and second outputs of which are , respectively, the output of the second register and the output of the decoder, the information input of which is connected to the output of the third register, the first and second information inputs of the third switch are connected to the outputs of the first and second switches, and the output is information-. the input of the second register, the first information input of the first switch is connected to the output of the first register, the second information input of the first switch and the information input of the first register are the third information input of the driver, the first and second information inputs of the second switch are the second and first information inputs, respectively driver, the first information input of the driver is connected to the information input of the third register, the control inputs of the first and second switch in interconnected. ft Qi m . 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