JPS57200999A - Memory circuit checking system - Google Patents

Memory circuit checking system

Info

Publication number
JPS57200999A
JPS57200999A JP56085266A JP8526681A JPS57200999A JP S57200999 A JPS57200999 A JP S57200999A JP 56085266 A JP56085266 A JP 56085266A JP 8526681 A JP8526681 A JP 8526681A JP S57200999 A JPS57200999 A JP S57200999A
Authority
JP
Japan
Prior art keywords
address
written
applying
counter
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56085266A
Other languages
Japanese (ja)
Inventor
Takuki Kishino
Masaaki Kobayashi
Shigeru Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56085266A priority Critical patent/JPS57200999A/en
Publication of JPS57200999A publication Critical patent/JPS57200999A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters

Abstract

PURPOSE:To easily detect a fault of an address line of a memory circuit, by working a test data to be written in a memory. CONSTITUTION:If a faulty place G (ground) exists in an address line A4, a binary data D2 to be written in addresses a16-a31 is written in address a0-a15. In such a state, when a data following the address a0 is read out by applying a pulse signal P1 to a counter 4 again, operating it, also applying the pulse signal P1 to an address counter 9, and also applying a read-out signal R to a reading- out circuit 8, an output value of the counter 4 does not coincide with an output signal of the reading-out circuit 8, therefore, a faulty place of an addressing circuit of a memory can be detected. EOR circuits 11-14 and a detecting part 15 compare and detect it.
JP56085266A 1981-06-03 1981-06-03 Memory circuit checking system Pending JPS57200999A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56085266A JPS57200999A (en) 1981-06-03 1981-06-03 Memory circuit checking system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56085266A JPS57200999A (en) 1981-06-03 1981-06-03 Memory circuit checking system

Publications (1)

Publication Number Publication Date
JPS57200999A true JPS57200999A (en) 1982-12-09

Family

ID=13853768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56085266A Pending JPS57200999A (en) 1981-06-03 1981-06-03 Memory circuit checking system

Country Status (1)

Country Link
JP (1) JPS57200999A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59215100A (en) * 1983-05-19 1984-12-04 Matsushita Refrig Co Check method of semiconductor memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59215100A (en) * 1983-05-19 1984-12-04 Matsushita Refrig Co Check method of semiconductor memory

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