JPS6030046U - data storage device - Google Patents
data storage deviceInfo
- Publication number
- JPS6030046U JPS6030046U JP12294783U JP12294783U JPS6030046U JP S6030046 U JPS6030046 U JP S6030046U JP 12294783 U JP12294783 U JP 12294783U JP 12294783 U JP12294783 U JP 12294783U JP S6030046 U JPS6030046 U JP S6030046U
- Authority
- JP
- Japan
- Prior art keywords
- data
- shift register
- digit
- storage device
- data storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Executing Machine-Instructions (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案の一実施例を示すもので、第１図はシステ
ム全体の概略構成を示すブロック図、第２図はタイミン
グチャート、第３図はアドレス制御部の詳細を示す回路
構成図である。
１・・・ＲＯＭ、２・・・ＲＯＭアドレス指定部、５・
・・制御部、６・・・アドレス変換部、８・・・アドレ
ス制御部、２１・・・タイミング信号発生回路、２４・
・・シフトレジスタ、２５・・・バッファ、Ｇ１．Ｇ２
・・・ゲート回路。
ｔｌ
１ＮＨ，ＨＮ ｓｕｓｎｏｕｎＮＥＪＵＭ−砕
φＲ
φイ
φ５
Ｓ２
−−−か
誓The drawings show one embodiment of the present invention; FIG. 1 is a block diagram showing a schematic configuration of the entire system, FIG. 2 is a timing chart, and FIG. 3 is a circuit configuration diagram showing details of the address control section. . 1... ROM, 2... ROM address specification section, 5.
...Control unit, 6...Address conversion unit, 8...Address control unit, 21...Timing signal generation circuit, 24.
...Shift register, 25...Buffer, G1. G2
...Gate circuit. tl 1NH,HN susnounNEJUM-ShatterφR φiφ5 S2
---Or oath
Claims (1)
Ｍ桁のシフトレジスタと、このシフトレジスタの最上位
桁にデータを書込む手段と、上記シフトレジスタの内容
を上記データの書込み後Ｍ−１桁循環シフトする手段と
、上記シフトレジスタの最下位桁に記憶されているデー
タのみを読出すデータ読出手段と、上記シフトレジスタ
をデータ読出し後１桁だけシフトする手段とを具備した
ことを特徴とするデータ記憶装置。In an information processing system, an M-digit shift register stores data for each digit, a means for writing data to the most significant digit of the shift register, and a means for writing data to the most significant digit of the shift register, and converting the contents of the shift register to M-1 digit after writing the data. It is characterized by comprising means for circularly shifting, data reading means for reading only data stored in the least significant digit of the shift register, and means for shifting the shift register by one digit after reading the data. Data storage device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12294783U JPS6030046U (en) | 1983-08-08 | 1983-08-08 | data storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12294783U JPS6030046U (en) | 1983-08-08 | 1983-08-08 | data storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6030046U true JPS6030046U (en) | 1985-02-28 |
Family
ID=30280830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12294783U Pending JPS6030046U (en) | 1983-08-08 | 1983-08-08 | data storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6030046U (en) |
-
1983
- 1983-08-08 JP JP12294783U patent/JPS6030046U/en active Pending
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