JPS62241037A - Microcomputer - Google Patents

Abstract

PURPOSE:To realize the sequential memory reading with no intervention of a CPU and also to shorten the time needed for a test, by using an I/O controller, an incrementer and plural switching devices. CONSTITUTION:The switching devices 11 and 12 are turned off and on respectively in a test mode and therefore the control of an I/O 1 is separated from an I/O decoder 2 and shifted to an I/O controller 10 which connects the I/O 1 and a data bus 14. While the prescribed value is set to the counter of an incrementer 9 as its initial value. Then the numeric value '1' is successively added to the counter of the incrementer 9 synchronously with the internal clock of a system. The output of the incrementer 9 is is applied onto an address bus 13 as an address signal via the device 12. This address signal is decoded by a ROM decoder 6 and the contents of a ROM 5 are successively head out and then supplied to the I/O 1 via the bus 14. Thus the memory test time can be shortened.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a one-chip microcomputer:
Particularly concerned with the means for reading out the contents of memory (for the 27th test).

[Conventional technology]

Figure 2 is a block diagram showing the configuration of a conventional microcomputer. In Figure 1, (1) is an input/output device.
, (2) is an I/O decoder (a decoder for address signals accessing input/output devices), +31 is a RAM (random access memory), and +41 is a RAM decoder (RAM
151 is a ROM (read-only memory), (6) is a ROM decoder (a decoder for address signals that access the ROM), (
7) is a CPU (central processing unit), 181 is a program counter, (13) is a common address bus, (i”i)
is a common data bus. In the following explanation, it is assumed that the item (5) is used as a program memory and the RAM+31 is used as a data memory.

Next, the operation of this microcomputer will be explained. FIG. 3 is a block diagram with signal flows added to explain the operation of the device shown in FIG. 2, and the same reference numerals as in FIG. 2 indicate the same parts.

The value of the program counter (8) is CPU +7
Suppose that the output at a certain point l: is a, although it changes sequentially under the control of step 1. a is sent out on the common address bus (13) as an address signal.The signal on the common address bus (13) is sent to the I/O decoder (2), RA
It is input to the M decoder (4) and the ROM decoder (6) in parallel, but since the address signal specifies ROM +51, only the pigeon decoder (6) takes this in and decodes it, and reads the specified address of ROM151. For example, A
Reads the command from the address. This instruction statement is CPU (7
), this reads the data at address D of RAM f3) and stores it in the accumulator (general-purpose accumulator).
Assume that the instruction is to write 2 (L in U +71) (provided).CPU +71 controls the program counter (8) by signal C, and sends address signal d on the common address bus (13). .address signal d
is decoded by the RAM decoder (4) and stored in RAM 13
), the data stored there (: is read out as a signal e onto the common data bus (14), and written into the accumulator (-) of the CPU 17+.

Next, the control of the signal f from the CPU +71 causes the program counter (8) to read out the address signal g, and the signal g is decoded by the ROM decoder (6) and flf51
The instruction text is read from the specified address, for example, address G. The instruction text is interpreted by CPU +71, and it is assumed that this is an instruction to write accumulator data to address J of l/Ofll. The CPU +71 controls the program counter (8) by the signal i (2), outputs the address signal j onto the common address bus (13), and uses the contents of the accumulator as a signal to output the address signal j onto the common data bus (14). The signals on the common data bus (14)
o +11, auxiliary M(3), and ROM +531 are input in parallel, but I/
Written to address J of O(1).

[Problem that the invention seeks to solve]

Conventional microcomputers are configured as described above, so RAM, k? When testing by continuously reading out the memory contents of a DM, etc., the reading must be controlled via the CPU, and as the memory capacity increases, the time required for memory testing becomes longer. there were.

This invention was made in order to solve the above-mentioned problems, and provides a microcomputer that can read out memory sequentially without using a CPU, thereby shortening the time required for memory testing. The purpose is to

[Means for solving problems]

In the device of this invention, there is an incrementer which is not controlled by the CPU (two) having a counter that increments in synchronization with the internal clock of the microcomputer, and a VO which controls all the data on a common data bus to be input to a specific vO1. In the test mode in which a memory test is performed, the output of the incrementer is input as an address signal on a common address bus (double input, and the data successively outputted from the memory 11111 times is sent to the specific I/O bus via the common data bus). It was controlled so that it was input to O.

[Effect]

Since it is possible to sequentially read from the memory and input a specific IloE without going through the CPU, the time for memory testing can be shortened.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. is an I/O control, and (11) and (12) are switching devices.

The incrementer (9) can be preset to a predetermined number as an initial value, and is equipped with a counter whose count increases by 1 in synchronization with the internal clock of this microcomputer. CPU (
7) The signal on the common data bus (14) is controlled to be outputted to both VOl without depending on the command.

The switching devices f (11) and (12) operate under program control, for example, and when a flag C two wheel rlJ, such as a test mode flag, is set, a test mode (two people, logic "0" is set) is set. During normal operation, the switching device (12) is turned off and the I/O control (12) is turned off. Same as device C
Two works.

When the test mode is entered, the switching device (11) is turned off (
2) is turned on, and the control of VO (13) is separated from the vO decoder and transferred to the I/O control (/O), and the I/O control (1O) connects l/Oil+ and the data bus (14). Connect.Incrementer (9)
After a predetermined value is set as an initial value in the counter, the numerical value 1 is sequentially added in synchronization with the internal clock of this system.

The output of the incrementer (9) is applied via a switching device (12) to an address bus (13) as an address signal; in the embodiment shown in FIG.
The programs decoded by the decoder (6) and stored in the ROM+51 are sequentially output. The output programs are sequentially input to the I/1) via the data bus and stored. For example, if Ilo +1) has a character display, the ROM that comes out of the bladder
The contents of +51 can be displayed as Ilo ill E.

In the above embodiment, the case of a test to read out the contents of the kIDM 151 has been described, but the same applies even if two or more bladders are exposed.If a parity check is performed during the bladder extraction, for example, the results of the parity check will be used. It is possible to judge whether it is good or bad.

〔Effect of the invention〕

As described above (2) According to this invention, in the test mode, C
Apart from the control of the PU, the contents of the ROM and RAM can be sequentially read out by two people.
The time required for testing can be significantly reduced (2).

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional device, and FIG. 3 is a block diagram of the device shown in FIG. 2 with signal flows added. Ill is I/O, (2) is VO decoder, (3) is Shi, M, +4) is ~Tomoe decoder, (5) is stratification, (61 is shoulder decoder, (7) is CPU, 181 is Program counter, (9) is incrementer, (/O) )t
Ilo:27) 0-/L/, (11), (12)
C switching device, (+3) is a common address bus, (14
) is a common data bus. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] Central processing unit (CPU), random access memory (R
In a microcomputer in which a read-only memory (ROM), a read-only memory (ROM), and an input/output device (I/O) mutually input and output data via a common data bus, an address signal is sent from the CPU onto a common address bus. A program counter to send, a RAM decoder, a ROM decoder, and an I/O decoder that decode the address signals on the common address bus mentioned above to access the RAM, ROM, and I/O, and predetermined numerical values are set as initial values. an incrementer that has a counter that is incremented by a value of 1 in synchronization with the internal clock of the microcomputer, and the contents of this counter are output as an address signal on the common address bus in synchronization with the internal clock; , an I/O control that controls signals on the common data bus to be input to the I/O regardless of instructions from the CPU; When the output of the program counter is output on the common address bus, the I/O decoder controls the I/O, and the output of the incrementer is output on the common address bus. When the output is above, the above I
A microcomputer comprising: a switching device that switches the I/O to be controlled by the I/O control.