JPS62243040A - Detecting system for runaway of program - Google Patents

Abstract

PURPOSE:To exactly detect a runaway caused by an access of an unused address, by writing used/unused address information in a dead area of a parity data write ROM, and detecting an access of an unused address. CONSTITUTION:When a read signal of a program ROM 2 is inputted to a parity ROM 4' through a ROM 2 and an OR gate 11, a program data from the ROM 2 is sent out to a mu computer 1 and a parity checking circuit 3, and from the ROM 4', a parity data and a used/unused data are outputted to a selector 9. From a terminal YA of the selector 9, 1 bit of the parity data is selected and sent out to the circuit 3, and from a terminal YB, 1 bit of the used/unused data is selected and sent out to an FF 10. By the circuit 3, the program data of the ROM 2 is brought to a parity check, and if it is abnormal, a parity error signal is outputted. From the FF 10, unused address access error signals of '0' and '1' are outputted, in case when an address is used, and in case when it is unused, respectively.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is applicable to microcomputer progera, small! 1
[Prior art 1] Fig. 3 shows a conventional runaway detection circuit in a microcomputer system.

1 is a microcomputer that centrally controls this system. Reference numeral 2 denotes a program ROM (read-only memory) in which a program necessary for system operation is stored, and the program read by address access via the address bus is transferred to the microcomputer 1 via the data bus. At the same time as being taken in, the program is input to the parity check circuit 3 at the same time as the program is checked for parity. A parity ROM 4 stores parity data necessary for performing a parity check, and this parity data is input to the parity check circuit 3. Reference numeral 5 denotes an A/V decoder that decodes only the upper address. Reference numeral 6 denotes a detection circuit that detects whether an unused address is being accessed based on the decode signal from the address decoder 5. . 7 is a switch for changing the settings of unused blocks in order to deal with the program capacity #, and 8 is a watch for checking whether the above-mentioned operation is being performed at a predetermined timing. It is a dog timer and is set/reset by a refresh signal output from the micro combinator 1.

[Problem 1 to be Solved by the Invention This conventional circuit has the following problems.

(2) If used and unused addresses coexist in one block, the unused address detection circuit 6 will not detect an abnormality even if an unused address is accessed.

■In the above case, there is a possibility that an abnormality is detected by the watchdog timer 8, but it is only detected due to an abnormal operation, and the cause cannot be determined, and the watchdog timer 8 is activated. There is a risk that the output will be erroneous.

(2) The address decoder 5 and switch 7 as described above are required.

An object of the present invention is to reliably detect runaway due to access to an unused address with a simple circuit configuration.

[Means for solving the problem 1 The parity ROM provided for the conventional parity check circuit has a smaller capacity than the program ROM, but
Due to the low cost of OM, in most cases program RO
A ROM with the same capacity as M is used, so an unused bit area remains in the parity ROM. In the present invention, focusing on this point, information on used/unused addresses is written in the empty area of the abnormality detection parity ROM in which program parity data is written, and the program parity check is performed and 7 sectors of unused addresses are detected. The apparatus includes first and second determination means for performing the following.

[Operation 1] With the above configuration, when a program is read, the first determination means performs a parity check of the program based on the data from the abnormality detection ROM, and the second determination means performs a parity check of the program every time an address is accessed. This prevents the program from running out of control by checking whether unused addresses are being accessed.

[Example 1 An embodiment of the present invention will be described below with reference to the drawings.

In Figure 1, the address space is 64 bytes, and the first 32 bytes (addresses 0000 to 7FFF) are ROM
Space, second half 32 bytes (address 8000 to FFFF
) is RAM (random access memory) space, and 25
6 shows a parity check circuit using a 6-bit ROM.

Note that the same parts as in the conventional example are given the same reference numerals, and explanations of the same parts will be omitted.

From the parity ROM 4', 4-bit parity data and used/unused data are input to input terminals A and B of the selector 9, respectively. This fu + -h Oha Fushishi L Todoroki Ql Yu? +Material Vat flags AO and Al are input as select signals, and this select signal selects one bit of the 4-bit signals input to input terminals A and B. output terminal YA
and YB, respectively.

The signal from the output terminal YA is input to the parity check circuit 3 as parity data, and the used/unused data output from the output terminal YB is input to the input terminal of the 7-lip 70-tub circuit 10.

The microcomputer 1 outputs ROM and RAM read signals ROMRD and RAMRD, and a RAM read/write signal RAHWR.
The OMRD signal is input to the program ROM 2 and the parity check circuit 3, and three signals ROMRD.

R to MR[l, RA4R is input as a latch signal to the parity ROM 4' via the AND gate 11, and to the clock terminal CK of the 7-lip 70-tube circuit 10 via the delay circuit 12.

It shows the memory map of ROM 4' in Pit 2Fial and Toki Paris.

D4 to D7 are parity data of the program ROM 2, and DO to D3 indicate used/unused addresses.

Next, the operation of the circuit with the above configuration will be explained.

(1) When accessing ROM space of 32 bytes in the first half.

At this time, RO which is the read signal of program ROM2
MRD is activated and this read signal ROMRD
is input to the program ROM 2 and the parity ROM 4' via the ANI gate 11, so that the program data output from the program ROM 2 is sent to the microcomputer 1 and the parity check circuit 3 via the data bus. . Further, the parity ROM 4' sends used/unused data to the selector 9 along with parity data. Due to the lower order signals AO and A1 input to the select terminal S of the selector 9,
One bit of the 4-bit parity data is selected and sent to the parity check circuit 3 from the output terminal YA. As a result, the parity check circuit 3 performs a parity check on the program data from the program ROM 2 based on the parity data inputted by the read signal ROMRD, and if it is abnormal, the parity check circuit 3 detects a parity error. A signal PER is output.

On the other hand, from the 4-bit used/unused data output from the parity ROM 4', 1 bit is selected by the selector 9 and sent out from the output terminal YB to the input terminal of the 7-lip 70-tub circuit 10, similar to the parity data. . This input used/unused data is latched by a latch signal input to the clock terminal CK of the 7-lip 70-tub circuit 10. As a result, the output terminal Q of the 7-lip-flop circuit 10 outputs an unused address access error signal ADER which becomes O if the address is a used address and becomes 1 if it is an unused address.

(2) When accessing the RAM space of 32 bytes in the latter half.

At this time, MRD or read/write is sent to the RAM read signal R.
By activating the write signal RAMWR, the same operation as in the previous item (1) is performed, and the parity check of the program data and used/unused addresses are detected, and the parity check circuit 3 outputs the parity error signal PER. The 7-rip 70-tub circuit 10 outputs an unused access error signal ^DER.

[Effect of the invention 1] As explained above, in this invention, every time a memory is accessed, data indicating used/unused addresses written in the security ROM is read out and checked. It becomes possible to detect the detection early and reliably.

[Brief explanation of drawings]

FIG. 1 is a system block diagram showing one embodiment of the program runaway detection system of the present invention, and FIG. 2 is a block diagram showing a main circuit of the parity ROM in FIG. 1. 1... Microcomputer, 2... Program R
OM, 3... Parity check circuit, 4'... Parity ROM, 9... Selector, 10... 7 lip-flop circuit, 11... AND date, 12... Delay circuit. Patent Applicant: Fuji Electric Co., Ltd. Agent Patent Attorney: Blue and White Blue and 2 other people
9 Address data Figure 3

Claims (1)

[Claims] (1) In a runaway detection method in a microcomputer system, an abnormality detection ROM in which data indicating used/unused addresses is written for each address as well as program parity data, and first and second determination means are provided. and when reading a program, the first determination means performs a parity check of the program based on data from the abnormality detection ROM, and the second determination means determines whether an unused address is accessed every time an address is accessed. This is a program runaway detection method that is characterized by checking whether or not the program has run away.