JPS62288947A - Information processing controller - Google Patents

Abstract

PURPOSE:To surely start a processing routine where trouble occurs, by inhibiting the output from a RAM and reporting the set start address of this processing routine if trouble occurs in the RAM. CONSTITUTION:If trouble occurs in a RAM 2, an error detecting circuit 4 reports this trouble to a CPU 1. The CPU 1 outputs a signal to access an interrupt table 7 in the RAM 2. This signal switches the output of an address decoder 10 to the low level. Consequently, a chip selector 11 outputs a signal S1 in accordance with the signal in the low level outputted from an FF 8 and that from the decoder 10 to inhibit the output from the RAM 2. The selector 11 outputs a control signal S2 also to make a driver 12 active. Then, the driver 12 reports the start address of a processing routine 3a, where trouble occurs, set to a setter 1A to the CPU 1. The CPU 1 starts the routine 3a in accordance with this start address to perform the processing after the occurrence of trouble.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] This invention provides that when a failure occurs in a storage device that can be read and written at any time, the central processing unit detects the failure and converts the memory into a read-only memory. The present invention relates to an information processing control device that jumps to the first address of a failure occurrence processing routine in a file and starts the failure occurrence processing routine.

[Conventional technology]

A conventional information processing control device of this type will be explained based on FIG.

Figure 3 is a configuration diagram of a conventional information processing control device. (hereinafter referred to as ROM), 4 is RA
An error detection device detects a failure when a failure occurs in M2; 5 is an included input line for notifying CPU of the failure when a failure is detected by the error detection device 4; 6 is a CPU I; RAM 2; ．． Address data control line for transmitting and receiving data between ROM3,
7 is an included table provided in RAM2 which sets the start address of the failure occurrence processing routine in order to start the failure occurrence processing routine when a failure occurs in RAM2, and 3a is a failure current processing routine provided in ROM3. It is Ruchits.

Next, the operation will be explained.

When a failure occurs in the RAM 2 including the included table 7, the error detection device 4 detects this failure and notifies the CPUI of this failure via the interwoven input line 5. When the CPUI detects this failure, it fetches the starting address of the failure occurrence processing routine from the included table 7 provided in the RAM 2.

Then, fetch from this interwoven table 7,
Based on the resulting start address, the CPU 1 jumps to a failure occurrence processing routine 3a provided in the ROM 3, starts the aforementioned failure occurrence processing routine, and performs processing after the occurrence of a failure.

[Problem that the invention seeks to solve]

In the conventional information processing control device, the starting address of the failure processing routine is known by referring to the included table 7 provided in the R, A, and M2 in which the failure occurs, so There was a problem that it was not guaranteed that the system would jump to the failure processing routine provided in the system.

This invention was made to solve the above-mentioned problem, and even if a serious failure occurs in RAM2, the ROM can be reliably
Set the starting address of the failure processing routine provided in a to C.
The purpose is to make it possible to notify the PUI.

[Means for solving problems]

Therefore, the information processing control device according to the present invention has RA
A setting section IA that sets the starting address of the failure occurrence processing routine 3a to be activated when a failure occurs in M2, and a setting section IA that prohibits output from RAM 2 when the above failure occurs and that is set in the above setting section IA. The present invention is characterized in that it includes a start address guarantee circuit IB and ' which informs the CPU 1 of the start address of the failure occurrence processing routine 3a.

[Effect]

When a failure occurs in RAM2, the start address guarantee circuit IB prohibits output from RAM2, and transfers the start address of the failure occurrence processing routine 3a set in the setting section IA to the CPU.
Let 1 know.

The CPUI jumps to the failure occurrence processing routine 3a provided in the RO'M3 based on the informed start address, starts this failure occurrence processing routine 3a, and performs processing after the occurrence of the failure.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of an information processing control device showing an embodiment of the present invention. In the figure, 1 to 7 and 3a are the same components as the conventional information processing control device, and IA is activated when a failure occurs. The setting section IB, which sets the start address of the fault occurrence processing routine, prohibits output from RAM2 when a fault occurs, and sets the start address of the fault occurrence processing routine set in the setting section as the "start address" that informs the CPUI. This is an address guarantee circuit.

Further, 8 is a flip-flop that outputs an L level signal when the error detection device 4 detects a failure that has occurred in the RAM 2, and 9 is a flip-flop that lights up when the flip-flop 8 outputs an L level signal. 10 is an address recorder that decodes the address outputted from the CPU 1 via the address data control line 6; 12 is based on the control signal S2 output from the chip selector 1). CPU 1
This is the driver who tells you.

Here, flip-flop 83 address record 10. Chip selector 1). The driver 12 as a whole constitutes a leading address guarantee circuit IB.

Next, the operation will be explained.

When a failure occurs in the RAM 2 including the included table 7, the error detection circuit 4 detects the failure,
outputting an interrupt signal via the included input line 5;
Notify the CPUI of this failure. Further, when an interrupt signal indicating a failure is output to the interwoven input line 5, the flip-flop 8 outputs an L level signal and the LED 9 lights up.

Here, the CPU learns of the failure of RAM2 by the interrupt signal outputted to Included via the input line 5, and learns the starting address of the failure occurrence processing routine 3a ('RAM2
A signal for accessing the included table 7 within the address data control line 6 is output. The signal output from address data control line 6 switches the output of address decode 10 to an L level signal.

Therefore, depending on the L level signal output from the flip-flop 8 and the level signal output from the address recorder 10, the chip selector 1) outputs the signal S1 and outputs the R level signal.
Output from AM2 is prohibited to prevent the CPUI from fetching the first address from included table 7 in RAM2, and control signal S2 is output to put driver 12 into an active state. When the driver 12 enters the active state, it notifies the CPUI of the starting address of the failure occurrence processing routine 3a set in the setting device IA.

The CPUI activates the failure occurrence processing routine 3a according to the notified start address, and performs processing after the occurrence of the failure.

In this way, when viewed from the CPU side, it means that the included table 7 in RAMZ is being accessed, but in reality, the included table 7 in RAMZ is being accessed.
The starting address set in A will be notified to the CPUI.

In this embodiment, the starting address in the setting device IA is set using a switch. Although this method allows the setting of the starting address to be changed to some extent, it is limited to the following:
It is limited only to the range that does not overflow when adding offset segments with the same numerical value.

Therefore, as a modified example, eight 4-bit shift registers are lined up in which the starting address is set and written in advance so that the starting address of the failure processing routine can be set freely, and the bits are shifted each time the CPU fetches the starting address. Logic may also be provided.

FIG. 2 shows an example of the logic of the setter IA for this purpose. In the figure, 13 is a shift register in which an 8-bit offset signal and a segment signal are written in the vertical direction; 14; moves the contents of shift register 13 to the left by 1 every time the CPU fetches the first address.
This is a shift line for shifting bit by bit.

By configuring the logic in this way, each time the CPU fetches the first address of the fault occurrence processing routine, the shift line 1
4, the start address set in the shift register 14 can be taken into the CPUI while being shifted to the left one pint at a time.

In this example, by freely rewriting the contents of the shift register, the failure occurrence processing routine can be placed at any location in the ROM, resulting in a highly flexible system.

〔Effect of the invention〕

As explained above, according to the present invention, there is provided a setting section for setting the starting address of a failure occurrence processing routine to be activated when a failure occurs, and an output from the storage device which can be read and written at any time when the failure occurs. and a start address guarantee circuit that notifies the central processing unit of the start address of the fault occurrence processing routine set in the setting section, so that the included address in the RAM in which the fault has occurred is The starting address of the failure occurrence processing routine can be known without referring to a table, and reliable activation of the failure occurrence processing routine can be ensured.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing another example of a setting device, and FIG. 3 is a block diagram of a conventional information processing control device. ■...CPU, 2...RAM, 3...ROM, 4
... error detection device, 5 ... included input line,
6...Address data control line, 7...Intbutt table, 8...Flip-flop, 10...Address decoder, 1)...Chip selector, 12...Driver, 3a...Failure Occurrence processing routine, IA...
- Setting device, IB...starting address guarantee circuit. Agent Masuo Oiwa (and 2 others) Figure 1 Figure 2 Figure 3 Procedural amendment (1st Jyosho 214th)

Claims (2)

[Claims] (1) When a failure occurs in a storage device that can be read and written at any time, the central processing unit detects the failure and starts the failure processing routine from the first address of the failure processing routine in the read-only memory. In the information processing control device, a setting section for setting a starting address of a failure occurrence processing routine to be activated when the failure occurs, and inhibiting output from the storage device which can be read and written at any time when the failure occurs; An information processing control device, further comprising: a start address guarantee circuit that notifies the central processing unit of the start address of the failure occurrence processing routine set in the setting section. (2) The first address guarantee circuit includes a flip-flop that outputs a signal indicating that a failure has occurred when a failure occurs;
An address decode that prohibits output from a storage device that can be read and written at any time by a signal for detecting the first address output from the central processing unit, and a signal output from the flip-flop and a signal output from the address decode. 2. The information processing control device according to claim 1, further comprising a driver that notifies the central processing unit of the starting address set in the setting section.