JPH0421123A - Fifo register - Google Patents

Abstract

PURPOSE:To previously recognize the using state of a memory by optionally setting up the set point of set data, comparing the set point with data stored in a memory, and when the data value exceeds the set data value, outputting a set output signal. CONSTITUTION:An address comparator 7 always receives writing and reading addresses, compares both addresses with each other, and when a dual port RAM 4 becomes an overflow state, outputs an overflow output signal and turns a write control circuit 5 to a write disabled state. In addition, the circuit 7 computes a difference between the writing and reading addresses and outputs the number of words stored in the RAM 4 as address comparing data. Comparators 10, 11 receiving the address comparing data compare the set-1 holding data and set-2 holding the data respectively stored in holding circuits 8, 9. When the address comparing data exceeds the holding data by the comparator 10, the set-1 output signal is outputted, and when the address comparing data are less than the holding data by the comparator 11, the set-2 output signal is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to FIFO registers, and particularly to FIFO registers having a memory usage status notification function.

[Conventional technology]

Most conventional FIFO registers have an overflow output signal to notify when all internal memory capacity is used, and an empty output signal to notify when no memory is used, as memory usage status notifications. Some of them had a half-full output signal to notify when the middle of the memory capacity was used.

[Problem to be solved by the invention]

With the conventional FIFO register mentioned above, the memory usage state can only indicate overflow and empty half-full states, so it is necessary to know in advance that it will become completely overflow state or completely empty state, and to prevent overflow and If empty prevention is desired, there is a problem in that a dedicated control circuit must be provided externally, which increases the mounting area of the device and increases the economic burden. Also, if you need to input or output meaningful data in units of several bits or bytes, it is important to note that there may or may not be enough free memory space for one unit, and that one unit of data has already been stored. Information such as whether or not the data is present is required, and therefore a new circuit for recognizing one unit of data must be provided, resulting in the same problem as described above.

An object of the present invention is to provide a FIFO register that can output an alarm at a predetermined threshold, without increasing the device mounting area, and by incorporating it, reducing the cost.

[Means to solve the problem]

The FIFO register of the present invention includes a dual port RAM having a write port and a read port, a write control circuit that controls an address when writing data to the dual port RAM, and the dual port RAM.
A FIFO having a read control circuit that controls a read address when reading data from M, and an address comparison circuit that compares the latest address of the write control circuit with the latest address of the read control circuit and outputs the result.
In the register, two holding circuits each set an arbitrary value as a threshold for detecting the amount of held data and hold it, and the amount of held data in the dual port RAM output from the address comparison circuit and the held data set in the holding circuit. This configuration includes two comparison circuits that compare the amount with the amount detection threshold and output an alarm.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The FIF○ register 1 includes a dual port RAM 4 having a write port 2 and a read port 3, a write control circuit 5 that controls the address when writing data to the dual port RAM 4, and a dual port RAM 4 that has a write port 2 and a read port 3. -RAM
A read control circuit 6 that controls the read address when reading data from J, an address comparison circuit 7 that compares the latest address of the write control circuit 5 with the latest address of the read control circuit 6, and outputs the result, and setting 1 data. A holding circuit 8.9 inputs the setting 2 data and stores the setting 1 held data and the setting 2 held data, respectively, and either the setting 1 held data or the setting 2 held data output from the holding circuits 8 and 9. Input one side and the address comparison data output from the address comparison circuit 7, respectively, and set 1.
Comparison circuit 10.1 that outputs the output signal and the setting 2 output signal
Consists of 1.

Next, the operation will be explained.

First, when the number of memory words of the dual port RAM 4 is m, n smaller than m is set in the holding circuit 8 as setting 1 data, and m-n is set in the holding circuit 9 as setting 2 data. This setting may be controlled directly from the outside by one pull-down control, or may be controlled by a microprocessor or the like.

Next, input data is input from the write port 2, and the write control circuit F! Input data is written to a predetermined address by the write control clock outputted by @5 and the write address. Next, the read control circuit 6 is activated, and output data is output from a predetermined address to the read port 3 using the read control clock and the read address.

On the other hand, the address comparison circuit f\37 always receives the write address and the read address, compares them, and outputs an overflow output signal when the dual port RAM 4 is in an overflow state, and outputs an overflow output signal to the write control circuit. 5
Also disables the write permission signal. Moreover, when it is in a completely empty state, an empty output signal is output, and the read control circuit 6 also disables the read permission signal. Further, the address comparison circuit 7 calculates the difference between the write address and the read address, and outputs the number of words currently stored in the dual port RAM 4 as address comparison data. Comparing circuits 10 and 11 that receive this address comparison data compare it with the setting 1 holding data and setting 2 holding data held in the holding circuit 89, respectively. As a result,
If the address comparison data exceeds the address comparison data in the comparison circuit 10, a setting 1 output signal is output. Similarly, comparison circuit 11
If the address comparison data is below, the setting 2 output signal is output.

In the case of this embodiment, since the setting 1 data is set to n, it is possible to know that an overflow is likely to occur before m - n words that overflow. Due to this signal, on the data input side of the FIFO register of the present invention,
Data writing can be prohibited.

Similarly, since the setting 2 data is set to m-n, it can be known that the word is likely to become empty before m-n words become empty. This signal causes the data output side circuit of the FIF○ register of the present invention to
The presence or absence of data for words can be notified, and it is possible to prevent data from being read even though m-n words have not been stored.

FIG. 2 is an explanatory diagram showing the relationship between set values and output signals in one embodiment of the present invention.

Setting 1 data and setting 2 data can be set to arbitrary values from when the dual port RAM 4 to which the empty output signal is output is empty to when the dual port RAM 4 to which the overflow output signal is output is full. By setting the setting 1 data, a setting 1 output signal is output, and by setting the setting 2 data, a setting 2 output signal is output.

〔Effect of the invention〕

As explained above, the FIFO register of the present invention can arbitrarily set the setting value of the setting data, and compares it with the number of data stored in the memory, and if it exceeds the setting data value, the setting output signal is sent. By outputting , the memory usage status can be determined in advance when input data and output data are meaningful data in units of several bytes, or when overflow or empty data is likely to occur.

In addition, the function equivalent to the FIF○ register of the present invention can be implemented using the conventional FIF○ register.
To realize this with an IFO register, it was necessary to build a logic circuit around the FIFO register, but using the FIFO of the present invention also has the effect of reducing the total cost including the mounting area and design cost. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is an explanatory diagram showing the relationship between set values and output signals of one embodiment of the present invention. 1...FIFO register, 2...Write port,
3...Reading port, 4...Dual port, 5
...Write control circuit, 6...Read control circuit,
7... Address comparison circuit, 8, 9... Holding circuit, 1
0゜1...Comparison circuit.

Claims (1)

[Claims] a dual port RAM having a write port and a read port; a write control circuit that controls an address when writing data to the dual port RAM;
A FIFO register having a read control circuit that controls a read address when reading data from the dual port RAM, and an address comparison circuit that compares the latest address of the write control circuit with the latest address of the read control circuit and outputs a result. 2, set an arbitrary value as the threshold for detecting the amount of retained data and hold each value.
and two comparison circuits that compare the amount of data held in the dual port RAM output by the address comparison circuit with a held data amount detection threshold set in the holding circuit and output an alarm. FIF featuring
O register.