JPH08194647A - External solid-state memory - Google Patents

Abstract

PURPOSE: To surely protect a memory and to report the error of an access system to the side of the main body of equipment by detecting abnormality in the state of access from the main body of the object equipment to the memory and outputting its detecting signal to the main body of the object equipment. CONSTITUTION: A memory card 12 provided freely attachably and detachably to a main body 11 of the object equipment exchanges data with the main body 11 of the equipment through a data bus line, a designated address is sent from the main body 11 of the equipment through an address bus line to the memory card 12, a row address strobe(RAS) signal is sent through a RAS line and a column address strobe(CAS) signal is sent through a CAS line respectively. Besides, an interrupting signal is sent from the memory card 12 through an interruption control line to the main body 11 of equipment. Then, a detecting circuit 22 provided inside the memory card 12 detects wrong access from the main body 11 of the equipment to a dynamic RAM (D-RAM) 21 and outputs its detecting signal to the main body 11 of the object equipment.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external solid-state storage device using a memory card as an external storage medium.

[0002]

2. Description of the Related Art Conventionally, in many portable terminals such as electronic notebooks, personal computers, word processors, etc., a memory card as an external storage medium can be mounted to further increase the storage capacity. there were. The memory card used in this type of device has various types of built-in memory, storage capacity, access method, mapping, etc., and is generally not compatible.

Therefore, in order to access this memory card, an information area indicating the configuration of the card is provided in the card, and the contents of this information area are interpreted by the main body of the device in which the memory card is mounted. The ones that are controlled by the above are becoming mainstream.

[0004]

However, when a memory card that is not intended for the device body is attached to the device body, even if an erroneous access is made from the side of the memory card side, in some cases Data may be read or written from the memory card in some cases, which may result in short circuit of signal lines, malfunction, memory data destruction, or the like.

The present invention has been made in view of the above circumstances, and an object of the present invention is to reliably protect a memory when an erroneous access method is adopted and to prevent an access method error from occurring in the main body of the device. It is to provide an external solid-state storage device that can notify the user.

[0006]

Means for Solving the Problems That is, the present invention is as follows: (1) A memory provided inside a casing detachably provided to a main body of a target device and an access state from the main body of the target device to the memory. And a detection means for detecting the abnormality and outputting the detection signal to the target device body. (2) In the above item (1), the memory is a dynamic RAM, and the detecting means is the dynamic R.
It has a latch circuit that stores the RAS signal to the AM and is reset by the CAS signal. When the latch circuit does not have the CAS signal to the dynamic RAM, the latch content is output to the main body of the target device. It is a thing.

[0007]

According to the configuration of the above item (1), when an erroneous access method is adopted, it is detected and immediately notified to the device main body side to stop the access to the memory and protect the memory. can do.

According to the configuration of the above item (2), especially when a dynamic RAM is used as a memory, it is possible to detect the case where an erroneous access method is adopted by utilizing the presence or absence of the RAS signal and the CAS signal. Therefore, the action of the above item (1) can be realized without increasing the number of connection terminals of the memory card and the device main body to which the memory card is attached.

[0009]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows its circuit configuration, where 11 is a device body and 12 is a memory card. And the apparatus body 11 and the memory card 12, the address bus lines, data bus lines, RAS (R ow A ddress S trob
e: a row address strobe) line, CAS (C olu
mn A ddress S trobe: column address strobe) line, write enable (WE) line, read enable (OE) line, interrupt control (In
t. ) Line, power supply (Vcc) line and ground (GN)
The signal lines of the D) line are connected.

That is, the device body 11 and the memory card 1
Data is sent to and received from the device 2 via a data bus line, and a specified address is sent from the device body 11 to the memory card 12 via the address bus line, a RAS signal via the RAS line, and a CAS signal via the CAS line. ,
A write enable signal is sent via the write enable line and a read enable signal is sent via the read enable line, and conversely, an interrupt signal is sent from the memory card 12 to the device body 11 via the interrupt control line.

In the memory card 12, a dynamic RAM (D-RAM) 21 as a storage element and this D-RAM are provided.
Detection circuit 22 for detecting erroneous access to RAM 21
And at least are provided.

The D-RAM 21 includes the address bus line, data bus line, RAS line, CAS line,
It is connected to a write enable line and a read enable line, and has a RAS line and a C line among them.
The AS line is also connected to the detection circuit 22.

In the detection circuit 22, the RAS signal from the RAS line is input to the clock terminal CK of the flip-flop (F / F) 24 via the buffer amplifier 23 and to the NAND circuit 25, respectively.

The F / F 24 is C from the CAS line.
The inverted signal obtained by inverting the AS signal by the inverter 26 is input to the reset terminal R, and the power supply voltage Vcc is input to the delay input terminal D.
The output signal from the non-inverted output terminal Q is input to the NAND circuit 25.

Then, the output signal of the NAND circuit 25 is used as an interrupt signal via the interrupt control line and the device body 1
It is sent to the 1 side. In the above-mentioned configuration, FIG. 2 illustrates an operation when the memory card 12 is attached to the correct device body 11 that matches the memory card 12.

That is, in FIG. 2, the device body 11 accesses the memory card 12 to access the D-RA in the memory card 12.
The respective signal waveforms when the data stored in M21 are read are shown. First, the device main body 11 first changes the RAS signal normally at the “H” level as shown in FIG. 2 level, and then the CAS signal, which is also normally at "H" level as shown in FIG. 2B, is set to "L" level with appropriate timing.

Further, in synchronization with the RAS signal and the CAS signal, the row address (Row) and the column address (Col) are sequentially output as shown in FIG.
As shown in (4), the read enable signal which is normally at "H" level is kept at "L" level until the RAS signal and the CAS signal are at "L" level.

In the D-RAM 21 in the memory card 12, a row address is sequentially input from the address bus as the RAS signal becomes "L" level, and then a column address is sequentially inputted as the CAS signal becomes "L" level. Then, after waiting for the read enable signal to go to "L" level, the data written in the address position designated by the row address and column address is read out as shown in FIG. Is sent to the device body 11 side.

In the meantime, in the detection circuit 22, the falling edge of the RAS signal is latched by the F / F 24, but the falling edge of the CAS signal that is input subsequently is inverted by the inverter 26 to be an inverted signal, and the reset terminal R is supplied. The latch contents are reset because they are input.

Therefore, the normal output terminal Q of the F / F 24
Output becomes "L" level, and since at least one input in the NAND circuit 25 is "L" level, the output as an interrupt signal to the device body 11 side maintains "H" level, especially The state is not generated, and the device body 11 side is informed that the memory card 12 is normal.

Next, the operation when the device body 11 accesses the memory card 12 by the wrong access method will be described with reference to FIG. That is, in FIG. 3, the device body 11 accesses the memory card 12 as a memory card using a static RAM to access the D-RAM 2 in the memory card 12.
1 shows waveforms of respective signals when the data stored in 1 is to be read.

First, the equipment main body 11 keeps the RAS signal (which is recognized as another signal for the static memory on the equipment main body 11 side) which is normally at the "H" level as shown in FIG. It is set to the “L” level, as shown in FIG.
As shown in (3), the CAS signal remains at the normal "H" level and is not changed.

Further, the device main body 11 performs address designation to the static RAM as shown in FIG. 3 (4) through the address bus, and normally becomes "H" level as shown in FIG. 3 (5). The read enable signal is set to the "L" level in accordance with the RAS signal.

In the detection circuit 22 of the memory card 12,
Since the CAS signal does not change and stays at "H" level, F /
The F24 is not reset, and the F / F24 latches the falling edge of the RAS signal and sends out a slightly delayed RAS 'signal from the normal output terminal Q to the NAND circuit 25 as shown in FIG.

In the NAND circuit 25, R from the F / F 24
Since both inputs become "H" level when the AS 'signal rises, the interrupt signal to the device main body 11 side is changed from the normal "H" level to "H" level from that time as shown in FIG. 3 (7). The device main body 1 indicates that an interrupt condition occurs and the access method to the memory card 12 is changed to "L" level.
It informs the 1 side.

Therefore, the device main body 11 side can recognize this and immediately stop the reading of data, which has been performed in the D-RAM 21 in response to the read enable signal as shown in FIG. 3 (6). Therefore, it is possible to surely prevent short circuit of the signal line, malfunction, data destruction of the D-RAM 21, and the like.

In the above embodiment, the RAS signal and CA
An example in which when the device main body 11 accesses the memory card 12 using the dynamic RAM depending on the presence or absence of the S signal for the memory card using the static RAM having a different access method, this is detected. However, on the contrary, when the device main body accesses the memory card using the static RAM to the memory card using the dynamic RAM having a different access method, this is detected. It is very easily conceivable that the explanation is omitted here.

[0028]

As described above, according to the present invention, the memory is surely protected when the wrong access method is adopted,
In addition, it is possible to provide an external solid-state storage device capable of notifying the device body side of an error in the access method.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the present invention.

FIG. 3 is a diagram for explaining the operation of the present invention.

[Explanation of symbols]

 11 ... Device main body 12 ... Memory card 21 ... Dynamic RAM (D-RAM) 22 ... Detection circuit 23 ... Buffer amplifier 24 ... Flip-flop (F / F) 25 ... NAND circuit 26 ... Inverter

Claims (2)

[Claims] 1. A memory provided inside a casing that is detachably attached to a main body of a target device, and an abnormality in an access state from the main body of the target device to the memory is detected, and a detection signal thereof is used as the target. An external solid-state storage device, comprising: a detection unit for outputting to an apparatus body. 2. The memory is a dynamic RAM, and the detection means has a latch circuit that stores a RAS signal to the dynamic RAM and is reset by a CAS signal, and the latch circuit is a CA to the dynamic RAM.
The external solid-state storage device according to claim 1, wherein the latch contents are output to the main body of the target device when there is no S signal.