JPS6170646A - Detection system for ineffective data - Google Patents

Abstract

PURPOSE:To easily decide whether data is effective or not by providing as RAM with a one-bit ineffective data indication bit for every word. CONSTITUTION:Normal data are written in and read out of the RAM1 after initial setting operation, but the indication bit of the ineffective data indication bit area 2 is still set to '0' until data is written in the corresponding address and when the data is written in the address, an indication bit input 20 is '1', so the indication bit is reset to '1' thereafter. Therefore, even when the corresponding address after the data written is read out with a readout signal 8 and an address 5, the indication bit is '1' and an indication bit output 21 is '1', so no ineffective data detection signal 6 is outputted from a gate 91.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an invalid data detection method for detecting that successive data of a random access memory that can be written to and written to continuously is invalid.

[Background of the invention]

Generally, the contents of a random access memory capable of storing and starting data are undefined after power is turned on.

Therefore, if you mistakenly read out contents in an undefined state after entering valid data and process them according to gfC, the result will be unpredictable. To deal with this problem, by initializing the contents of the memory to a certain value in advance, it is possible to limit the processing to be performed in the event of erroneous reading. However, this conventional method has the problem of detecting the occurrence of erroneous reading and finding the address where the erroneous reading occurs.

In addition, when random access memory is used as a data buffer and data writing and reading are repeated, there is a possibility that erroneous reading may occur even outside of the initial setting operation when valid data has not been written. . In this case, the above-described detection method based on initialization is ineffective.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide an invalid data detection method that detects reading out the contents of a random access memory in which no valid data has been written and notifies the outside. .

[Summary of the invention]

The present invention provides an invalid data display bit area of 1 bit for each word in a random access memory that can be written and read, and determines whether the contents of the word are in an invalid state after writing valid data or in a valid state after writing. This is an invalid data detection method that detects reading of invalid data before writing by displaying this and enables notification using an external button.

[Embodiments of the invention]

An embodiment of the FK invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing an embodiment of an invalid data detection method according to the present invention. In FIG. 1, 1 is a writable and readable random access memo 9%, and 2 is an invalid data display bit area of 1 bit for each food provided in the memo 9. Reference numerals 20 and 21 are the display bit manual output and the public display bit output of the invalid data display bit area 2, respectively. 3 is Fujitsubu flop, 61 and 3
2 is a set signal and a reset signal for the flip-flop 30, 4 is a decoder, and 5 is an address to the random access memory 1, invalid data display bit area 2, and decoder 4, respectively. Reference numeral 6 designates an input signal, 7 a human output access instruction signal, 8 a read signal, 9 an invalid data detection signal, and 91 a gate.

Next, the operation of the circuit shown in FIG. 1 will be explained. First, the initial setting operation is to input the input/output access instruction signal 7 simultaneously with the input/output access instruction signal 7 after the power is turned on, and manually press the decoder 4 button with the pre-specified address 7 address 5. When Pflo and P3 are reset, the display bit input 20 becomes 10''. In this state, by inputting the pledge signal 6 and address 5 to all addresses in the invalid data display bit area 2, the invalid All data display bit areas 2 are set to 10''. By inputting the input/output access instruction signal 7 and another address specified in advance to the decoder 4 as the address 5, the shift signal 31 from the decoder 4 is used. When the flip-flop 6 is set, the display bit input 2o becomes open.

The above is the initial setting operation, and the input signals and addresses may be created by known hardware logic (not shown), or may be created by an initialization program in a process (not shown), f, and a memory dedicated to setting out.

After the above initial setting operation, normal data is written and read from the random access memory 91.
At this time, the display bit of invalid data display bit area 2 is 10'' until data is written to the address.
' remains set, and if data is written to the address even once, the display bit input 20 becomes 1.
Since it is in the state of 1'', it will be reset to 11'' thereafter.

Therefore, even if the address after data writing is read using the read signal 8 and the address 5, the display bit is 11'' and the display bit output 21 is 11'', so the invalid data detection signal 9 from the gate 91 is not output. . However, if the address in the data folded state is mistakenly read by the read signal 8 and the address 5, the display bit output 21 is '0' at the display bit 10'', so the invalid data detection signal 9 from the gate 91 is output. is sent out and notified to the outside.For example, main detection store number 9 accesses random access memory 1, and by using it as an interrupt input to f, it performs appropriate processing after invalid data reading occurs. Is possible.

As described above, according to this embodiment, when an address whose content is an undefined value after power-on is read out by mistake in the random access memo 91, this can be detected and notified to the outside.

FIG. 2 is a schematic diagram showing an embodiment of the invalid data detection method according to the present invention. In FIG. 2, the same reference numerals or symbols as in the OFF diagram indicate the same or corresponding parts, 10 is a delay circuit, 11 is a delayed write signal, 12 is an AND gate, 13 is a gate, and 14 is an OR gate.

Next, the operation of the circuit shown in FIG. 2 will be explained. First, the initial setting operation is 79. After resetting the flip-flop 3 and setting all the invalid data display bit areas 2 to '0'', the process is the same as in FIG. 1 until the flip-flop 3 is set. Then, when the flip-flop 3 is set,
Since the input from the AND gate 12 to the delay circuit 10 is prohibited, the delayed write signal 11 remains at ``0'''', and FIG. 2 becomes equivalent to FIG. 1.

Therefore, if normal data is written and successively output to the busy random access memo J'IK after the above initial setting operation, the value of the display bit output 21 corresponding to the data writing or non-writing state as shown in FIG. In response, invalid data detection signal 9 is not sent or is sent. However, when the contents of the random access memory 1 are read out using the 1 read signal 8 and the address 5 after resetting the flip-flop 5, the invalid data detection signal 9 is either not sent or sent, depending on the value of the display bit output 21. , display bit, ) Since the input to the delay circuit 10 from the AND gate 12 is 11'', regardless of the value of the output 21, the delayed write signal 11 (11'') is generated, which causes the input from the AND gate 13 to be 11''. The read signal 8 to the invalid data display bit area 2 is prohibited, and instead, the honor signal 6 from the OR gate 14 to the same area 2 is sent, and the display bit y) is input 20 at t'0.
” is set in the corresponding address of R station data display bit area 2. The display bit of the relevant address in the busy invalid data display bit area 20 is set to #oM, and the unwritten address becomes t#.

In addition, the above delay-J! f! The delay time 10 is set to be longer than the time required for the young gator detection signal 9 to be recognized externally. If the write operation is performed again with the flip-flop 3 reset, the address in the invalid data display bit area 20 will be set to 10'' again, so immediately before the glance operation, 79:, Pflo, and P3 are
It is better to leave it set.

As described above, according to this implementation, even areas that should be regarded as invalid data once data is read out, such as the goo-tapa and fa areas of the random access memory 1, are treated as invalid data until the next data is written into the iF. I am confident that I have read out the .

In the embodiment shown in Figure 2, invalid data is displayed.

Initialization of bit area 2 The flip-flop to set the address to 10'' in bit area 20 and the flip-flop to set the address to #oM are shared. However, they can be separated.

Further, in the embodiments shown in FIGS. 1 and 2, the meanings of the display bits 10'' and 11'' in the invalid data display bit area 2 can be interchanged to configure a circuit.

〔Effect of the invention〕

As is clear from the above explanation, firstly, random access memory! When the contents are erroneously read out after inputting the contents, it can be detected at that time and notified to the outside, thereby making it possible to configure a system that performs arbitrary processing when erroneous reading occurs. Second, in addition to the above, even in cases where the contents are invalid until the next data is written, such as in data files, once the contents are read, it is detected that the invalid data has been read. It is possible to notify the outside party.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the invalid data detection method according to the present invention, and FIG. 2 is a diagram showing a similar embodiment of the invention. 1...Random access memory, 2...Invalid data display bit area, 3...Fuji, puflo, puf, 4...
Decoder, 5... Address, 6... Commitment signal, 7
... input/output access instruction signal, 8... continuation signal,
9... Invalid data detection signal, 10... Delay circuit, 1
1...Delayed write signal.

Claims (1)

[Claims] 1. A writable and readable random access memory is provided with a 1-bit invalid data display bit area for each word, means for setting a display bit in the display bit area, and means for setting a display bit in the display bit area; An invalid data detection method comprising: means for detecting and notifying the outside when a certain address continues to be written; and means for resetting a display bit of the address when writing to the address occurs. 2. Providing a 1-bit invalid data display bit area in word units in a random access memory that can be written and read continuously, means for setting a display bit in the display bit area, and reading an address where the display bit is set. A means for detecting and notifying the outside when a write occurs, a means for resetting a display bit of the address when writing to a certain address occurs, and a means for reading a certain address for which the display bit is reset. An invalid data detection method comprising means for setting the display bit after successively displaying the contents of the address when the address is read.