KR19980072825A - Semiconductor memory device and method for discharging bit line thereof - Google Patents

Abstract

A semiconductor memory device according to the present invention includes an array for storing data, and the array includes a plurality of cells formed in a region where rows and columns intersect each other, and a plurality of bit lines are electrically connected in a column direction of the array. And an address transition detection circuit that receives an address applied from the outside, detects that the state of the address changes, and generates a pulse signal according to the result, and a predetermined bit line corresponding to the address to a predetermined level. A precharge control circuit for generating a precharge signal in response to the pulse signal, a sensing control circuit for generating a sensing signal for sensing data on the selected bit line in response to the precharge signal, for precharging; Receiving the detection signal and detecting a falling edge of the detection signal; And a bit line discharge control circuit for generating a discharge signal for the selected bit line room cell.

Description

Semiconductor memory device and method for discharging bit line thereof

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having an immunity to external noise and a bit line discharge method thereof.

In general, as the semiconductor memory device is highly integrated and low in power, the operation of the device is controlled by using an address transition detection circuit (ATD circuit) in the semiconductor memory device. The outputs of ATD circuits are mainly the signals related to sensing in the sense amplifier and the circuits involved in data latches, output buffers, and bit line discharges.

The reason for the device's bit line discharge is to charge the bit line in order to sense the data in the read cycle of the previous stage. If this is not possible, fail data may be read due to coupling between bit lines.

1 is a block diagram showing the configuration of a semiconductor memory device according to the prior art. In FIG. 1, a semiconductor memory device includes an array 10, an address trantion detection circuit (ATD circut) 11, a precharge controlling circuit 12, and a sensing control circuit. (sensing controlling circuit) 13, bit line discharge decoder 14, and sense and amp circuit 15. The ATD circuit 11 detects a state transition of an address applied from the outside, generates a pulse signal SUM according to the result, and generates a discharge signal ΦVdis having the same phase. The precharge control circuit 12 generates a control signal? CON and a precharge signal? PRE in response to the pulse signal SUM. The sensing control circuit 13 generates a sensing signal CESA2 for sensing cell data on a selected bit line in response to the control signal Φ CON and the precharge signal Φ PRE. In addition, the bit line discharge decoder 14 may include addresses Ai and ( ), (Aj) and ( ), (Ak) and ( ) Is input to generate a signal Bdisj for discharging the selected bit line in response to the discharge signal .phi.dis. 2A through 2C are circuit diagrams showing detailed circuits of the ATD circuit 11, the precharge control circuit 12, and the sensing control circuit 13 of FIG. 1. 3 is a circuit diagram showing a detailed circuit of the bit line discharge decoder 14 of FIG. In Fig. 3, addresses Ai and ( ), (Aj) and ( ), (Ak) and ( ) Are combined with each other to select only one bit line. When the discharge signal Φdis is at a low level, the Bdisj signal is formed to discharge all the bit lines except the selected bit line, and conversely, the discharge signal Φdis If) is high level, all bit lines are configured to be discharged. 4 is an operation timing diagram according to the prior art.

Typically, the discharge for these bit lines is done before precharging the corresponding bit lines by the ATD signal. In this case, there is no problem when the input address shows a normally stable waveform. However, if a certain amount of noise pulses occur in the system after a certain period of time after the input has successfully transitioned, the ATD circuit has two reactions.

First of all, input noise causes the trip of the input buffer to be ensured. In this case, the ATD signals generated in the chain form due to the input transition are generated normally. Is reactivated and data latched to the output can output good data without any problem.

Second, this is the case when the input noise has an ambiguous level that cannot ensure high to low or low to high transitions in the input buffer. Some of the signals at the front end are not perfect, but they operate momentarily, while the signals at the rear end are not affected by noise at all, causing the fail data to latch, causing a malfunction. If φdis is the control signal of the bit line discharge, this is the case. If φdis is formed again by noise while the bit line discharge is normally performed and the sense amplifier performs sensing over the precharge period, data sensing is performed. Discharging the bit line is causing the sense amplifier to sense fail data.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and a semiconductor memory device and a bit thereof, which discharge a bit line using a signal obtained as a result of detecting a falling edge of a sensing signal generated from a sensing amplifier circuit. To provide a line discharge method.

1 is a block diagram showing a configuration of a conventional semiconductor memory device;

FIG. 2A is a circuit diagram illustrating an ATD circuit of FIG. 1;

FIG. 2B is a circuit diagram illustrating a precharge control circuit of FIG. 1;

2C is a circuit diagram illustrating a sensing control circuit of FIG. 1;

3 is a circuit diagram illustrating a detailed circuit of the bit line discharge decoder of FIG. 1;

4 is an operation timing diagram according to the prior art,

5 is a block diagram showing a configuration of a semiconductor memory device according to the present invention;

6A is a circuit diagram illustrating an ATD circuit of FIG. 5;

6B is a circuit diagram illustrating a precharge control circuit of FIG. 5;

6C is a circuit diagram illustrating a sensing control circuit of FIG. 5;

6D is a circuit diagram illustrating a bit line discharge control circuit of FIG. 5;

7 is an operation timing diagram according to the present invention;

* Explanation of symbols for main parts of the drawings

10: array 11, 20: ATD circuit

12, 22: precharge circuit 13, 23: sensing control circuit

14, 25: bit line discharge decoder 24: bit line discharge control circuit

15, 26: sense amplifier

According to one aspect of the present invention for achieving the above object, an array for storing data, and the array is composed of a plurality of cells formed in the region where the rows and columns intersect, the column direction of the array A bit line discharge method of a semiconductor memory device in which a plurality of bit lines are electrically connected to each other, the method comprising: detecting a transition state of an address applied from the outside and precharging a predetermined bit line corresponding to the address to a predetermined level; And generating a sensing signal for sensing cell data on the selected bit line, and detecting a falling edge of the sensing signal to discharge the selected bit line.

Another object of the present invention is an array for storing data, the array is composed of a plurality of cells formed in an area where the rows and columns intersect, a plurality of bit lines are electrically connected in the column direction of the array, Means for receiving an address applied from the outside, detecting the state of the address transition, generating a pulse signal according to the result, and precharging a predetermined bit line corresponding to the address to a predetermined level, Means for generating a precharge signal in response to the pulse signal, means for generating a sensing signal for sensing data on the selected bit line in response to the precharge signal, and receiving the sensing signal, the sensing A discharge signal for detecting a falling edge of the signal to discharge the selected bit line Means for generating a.

By such an apparatus and method, the immunity to external noise can be improved.

Hereinafter, reference will be made in detail with reference to FIGS. 5 to 7 according to an embodiment of the present invention.

5 is a block diagram illustrating a configuration of a semiconductor memory device according to an exemplary embodiment of the present invention. In FIG. 5, the semiconductor memory device of the present invention includes an array 10, an address transition detection circuit 20, a precharge control circuit 22, a sensing control circuit 23, and a bit line discharge controlling circuit. circuit 24, a bit line discharge decoder 25, and a sense amplifier circuit 25. The array 10 is for storing data and includes a plurality of cells formed in an area where a row and a column cross each other and include a plurality of bit lines BL0,... In the column direction of the array. (BLi) is electrically connected. The ATD circuit 20 detects a state transition of an address applied from the outside and generates a pulse signal SUM according to the result. The precharge control circuit 22 generates a control signal? CON and a precharge signal? PRE in response to the pulse signal SUM. The sensing control circuit 23 generates a sensing signal CESA2 for sensing cell data on a selected bit line in response to the control signal Φ CON and the precharge signal Φ PRE. The bit line discharge control circuit 24 detects the falling edge of the detection signal CESA2 when the detection signal CESA2 is applied, and generates a discharge signal Φdis according to the result. In addition, the bit line discharge decoder 25 may include addresses Ai and ( ), (Aj) and ( ), (Ak) and ( ) Is input to generate a signal Bdisj for discharging the selected bit line in response to the discharge signal .phi.dis.

6A through 6D show circuit diagrams showing detailed circuits of the ATD circuit 20, the precharge control circuit 22, the sensing control circuit 23, and the bit line discharge control circuit 24 of FIG. 5. . 7 is an operation timing diagram according to the present invention. The operation according to the present invention will be described below with reference to Figs.

When an address is applied from outside to read cell data held by a predetermined cell, the ATD circuit 20 of FIG. 5 detects a transition state of the address and generates a high level pulse signal SUM. Subsequently, the precharge control circuit 22 generates a precharge signal Φ PRE which transitions to a low level in order to precharge the bit line corresponding to the address to a predetermined level in response to the pulse signal SUM. In addition, a control signal Φ CON is generated. Subsequently, the sense amplifier 26 which receives the precharge signal Φ PRE receives the corresponding bit line to a predetermined level. In addition, the sensing control circuit 23 receiving the precharge signal Φ PRE outputs a sensing signal CESA2 that is activated for a preset time for sensing cell data transferred on the precharged bit line. The bit line discharge control circuit 24 receiving the sensing signal CESA2 detects the falling edge of the sensing signal CESA2 and generates a discharge signal Φ 6dis according to the result. Finally, the bit line discharge decoder 25 may include addresses Ai applied from the outside and ( ), (Aj) and ( ), (Ak) and ( ) Is input to generate a signal Bdisj for discharging the selected bit line in response to the discharge signal .phi.dis. When the discharge signal? Dis is applied at a low level, all of the bit lines except for the selected bit line are discharged. When the discharge signal? Dis is applied at a low level, all of the bit lines are discharged. If the discharge signal Φdis is driven by some noise at the time when the detection signal CESA2, which is the activation period of the sense amplifier 26, is at a high level, the bit line level being sensed is dropped, and the data read fail. This will occur. However, as shown in FIG. 7, the discharge signal Φdis is generated by receiving the falling edge of the sense signal CESA2 (that is, the edge at which the sense amplifier is deactivated) without configuring the discharge signal Φdis in front of the ATD circuit 20. Therefore, no noise occurs because a pulse signal is not generated in the case of noise that can not trip the input even if noise is generated. Even if the input is tripped, the discharge of the selected bit line occurs in a state where the sense amplifier 26 is not operated, so that data reading is not a problem at all.

As described above, when a signal for discharging the selected bit line is used as a signal for detecting the falling edge of the sensing signal, which is an output of the sensing control circuit, instead of being generated from the ATD circuit, a fail is generated when data is read to external noise. Can be prevented.

Claims (2)

An array for storing data, and the array is composed of a plurality of cells formed in an area where a row and a column cross, a bit line discharge of the semiconductor memory device electrically connected to the plurality of bit lines in the column direction of the array A method, comprising: detecting a transition state of an address applied from the outside, precharging a predetermined bit line corresponding to the address to a predetermined level, and sensing signals for sensing cell data on the selected bit line And discharging the selected bit line by detecting a falling edge of the sensing signal. An array for storing data, and the array is composed of a plurality of cells formed in an area where a row and a column intersect, a plurality of bit lines are electrically connected in the column direction of the array, the address is applied from the outside Means for detecting that the state of the address transitions, generating a pulse signal according to the result, and precharging a predetermined bit line corresponding to the address to a predetermined level in response to the pulse signal. Means for generating a precharge signal, means for generating a sensing signal for sensing data on the selected bit line in response to the precharge signal, and receiving the sensing signal to detect a falling edge of the sensing signal. Means for generating a discharge signal for discharging said selected bit line. Semiconductor memory device.