JPS60189047A - Data processing device - Google Patents

Abstract

PURPOSE:To shorten the testing time of an incorporated RAM by providing a switching circuit through which data can be transferred directly from an input/output port to the RAM or from the RAM to the input/output port. CONSTITUTION:In case of testing of a RAM3, a micro instruction to write data on an internal bus 8 onto an address position indicated by a program counter 4 is sent to a CPU1 from an external test device 10 through an input/output port 6. Then, the micro instruction is read out, and the start address of the RAM3 is set to the counter 4 by a control signal outputted from the CPU1. Simultaneously, a switching circuit 11 is switched to make it possible that data is transferred directly from the input/outut port 6 to the RAM3 through the bus 8, and the RAM3 is set to the write state by a write signal from the CPU1. Thereafter, contents of the counter 4 are counted up or down for every one cycle by the signal from the CPU1, and contents of the RAM3 are outputted to the bus 8 successively.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a data processing technology and a technology that is particularly effective when applied to a data processing integrated circuit having a built-in storage device. The present invention relates to technology that is effective for use in data processing devices such as built-in single-chip microcomputers (hereinafter referred to as single-chip microcomputers).

[Background Art] In data processing integrated circuits such as single-chip microcomputers that have a built-in RAM (random access memory) that can be written to and read out at any time, there is a single pin in the RAM.
~In order to detect whether there is a defect or word line defect, an appropriate test pattern is input into the CPU (microprocessor) from the outside, and the internal CPU repeats the row 1 instruction and store instruction. In return, the built-in R and AM are tested by repeatedly writing the dead pattern into the RAM and reading it out.

However, the row I instruction and store instruction by the CPU are
Since each test pattern takes 3 to 4 cycles, it takes a total of 7 to 8 cycles to write and read a 1-by-1 test pattern to and from the RAM.

By the way, for example, the conventional 1-I D 6 manufactured by Ikkotachi Manufacturing Co., Ltd.
In a single-chip microcontroller like 801, 128
It just had a small built-in RAM like the one in the Buy 1~. Therefore, even if there is an eggplant method in which load and store instructions can be repeated using CI)U, the testing time may not be that long due to the small capacity of 1〈ΔM. That wasn't it.

However, it is expected that the capacity of RAM built into single-chip microcomputers will gradually increase in the future. Therefore, if the CPU was used in the past to write and read the test pattern in the RAM, which took 6 to 7 cycles per byte, the R
, There is a risk that testing time will increase significantly as the capacity of AM increases.

In particular, in the RAM testing method θ;
There are some cases that require a test IL'7 proportional to the square of the number Pi1-2. If such a testing method is adopted, RA! vl capacity is 2
If it doubles, the Nastin 911.1 period will quadruple, and R
If the capacity of AM increases by 4 times, the testing time will increase to +6-7s, ゛, and so on.
The testing time increases in proportion to the square of the sum of f'J. Furthermore, there is a disadvantage that the greater the number of cycles per high to 1, the more 11 of the necessary dead pattern will be required.

[Purpose of the Invention: ``One object of this invention is a data processor with a built-in ΔM like a single-chip microcomputer.'' 11 Device 1. The purpose of this test is to shorten the interval between 'i' and 'i'.

Another object of the present invention is to add a new data processing function to a data processing device with a built-in history Δivl.
′! The purpose is to make sure that

The above-mentioned and other objects and novel features of the present invention will become clear from the description of this specification, parts 1 and 1, and the accompanying drawings.

[Summary of the Invention] Among the inventions finally disclosed in the present application, representative inventions (to give a brief description of the invention, the following are one).

That is, for example, in the middle of the data bus in the data processing device 1 with built-in RA:'Vl, there is a
Send the data directly to the concubine, and send it to the concubine from RA1 to the concubine 1~(; Cut 4'jj 4 circuits into 1 (
For ψ, data is once transferred to the internal register by ('; :)L), and from 9 to I(ΔM or crowd capo-1 to
Follow the order of P that sounds like ni・i
Turn on the J switching circuit 7. 'E, by directly transferring 1 (from HA M to KAPO-1- or conversely from KAPO-) to 1 (ΔMj- data, 1 pie 1~1~ in 1 cycle, respectively) The pattern can be written to and read from RAM for test 1 of the test, greatly shortening the testing time and reducing the Cl
) By combining with burst instructions, address registers, etc. that read data from memory without going through U,
1) It is possible to easily add new functions such as data processing such as MA transfer.

The present invention will be explained in detail in the following examples and examples.

[Example 1] No. 11-1 shows an example in which the present invention is applied to a zincle chip microcomputer, and the part surrounded by the chain line in the figure is a single semiconductor substrate such as silicon. A rainbow is formed.

The single-chip microcomputer MI) of this embodiment,
Although not particularly limited, J is a CPU which controls the internal execution units 1 to 1, etc. in accordance with Brothalum, and the operating programmer 13, etc. of this CPU 1 are stored] 2.0
M (read only memory) 2, mainly CP'U
]Provides a work area for the history ΔM3, a program counter 4 that holds the address of the next command or data to be read, a timer 5, an input/output capo 1-0, a serial number 107, etc., which connect the internal bus 8. are connected to each other through.

Further, a dest device 10 is connected to the single-chip microcomputer MPU via an external bus 9 connected to an input/output port.

The CPU 1 has an instruction register in which program instructions are sequentially fetched, and a micro register (OM,
It is composed of a control decoder that decodes the nine microinstructions read from the micro ROM and forms control signals, an execution unit 1 consisting of various registers such as an accelerator, AL, U (arithmetic logic unit), etc. ing.

In this example, the crowd capo-1-6 and CI) U
A switching circuit 11 is installed in the middle of the internal bus 8 that connects the RAM 3, RAM 3, etc.
is provided. This switching circuit 11 is CP tJ
It is controlled by the control signal output from 1), and there is a route for transferring data from the input/output side to CPtJl, and a route for transferring data from ROM 2 and RAM 3 side to CPUI.
The configuration is such that the state can be switched to enable each of the three routes 1--, which is route 1- for transferring data to RAM 3, and route 1- for directly transferring data from input/output capotro to RAM 3.

In addition, in this embodiment, the program counter 4 is incremented from 1 to 1 or decremented from 1 to 1 in the micro ROM in CI) tJl, and the ROM
] Or, it is possible to put the RAM 3 in a read state, output the data at the address position indicated by the program counter 4 to the internal bus 8, and output the data on this internal bus 8 to the external bus 9 via the input/output capotro. A macro instruction (burst instruction) to increment or decrement the program counter 4 and transfer the data on the external bus 9 to the internal bus 8 via the input/output capo 1-6. A macro instruction (reverse burst instruction) for storing the data on the internal bus 8 at the address location indicated by the program counter 4 at the same time when the RAM 3 is in a write state is stored. A control system is configured.

Therefore, in order to test the internal RAM3 in the single-chip microcontroller of this embodiment,
For example, a reverse burst command is input from the external test device 10 to CI) Ul via the input/output capo-1-0. Then, the corresponding microinstruction is read out and CI) U
The program counter 4 is set to the first address of the RAM 3 by the control signal outputted from the program counter 1. Further, the switching circuit 11 is switched by a control signal from C1) tJl, and data can be directly transferred from the input/output capo 1-6 to the RAM 3 via the internal bus 8.

By the Ryle signal output from CP tJ,
l(AM3 is put into write state. Then CP
The program counter 4 is incremented from 1 to 1 or decremented to 1 every cycle by a signal from U, and the contents are successively outputted to the address bus (internal bus 6).

Therefore, in synchronization from the test device 10 to the system t1,
If you insert test patterns one after another, it will take 1 cycle to
One dest pattern consisting of by 1- is written to the address position in the RAM 3 indicated by the program counter 4 at that time.

Furthermore, if a burst command is input from the dest device 10 to the CPU 1 after the writing of the test pattern to the RAM 3 is completed, the corresponding micro-instruction is read out and decoded to form a control signal, and this control signal As a result, the program counter 4 is incremented or incremented from 1 to 1, and the RAM 3 is placed in a read state, so that the data at the address location indicated by the program counter 4 is output onto the internal bus 8.

Also, the output buffer 12 is driven by a control signal from CPIJI, and the data on the internal bus 8 is transferred to the input/output port.
It is output to the external bus 9 via the trolley.

Therefore, it becomes possible to read one byte of data from the RAM 3 in one cycle and send it to the external tester 10. As a result, the testing time for the built-in JAM3 is significantly reduced.

In addition, since patterns can be written and read from 1 high 1 and test 1 in one cycle, there is no need for a pattern that commands a load command 11 store command for CI The amount of dead patterns can also be reduced. Therefore, it becomes easy to create a pattern for test 1, and the capacity of the Nast device can also be reduced.

Moreover, according to the above embodiment, in addition to testing AM3, a test pattern of l high 1- can be applied to registers inside a single-chip microcomputer such as the registers in the timer 5 and the serial 1107 in one cycle. Since writing and reading can be performed, testing of the internal register lfi can be done in a short time.

Furthermore, an address register is provided inside the CPU L, and an appropriate address (first address of transfer data) is set in the program counter 4, and another appropriate address (71~res) (last address of transfer data) is set in the address register. After setting the hair, execute the instruction or reverse burst instruction to berth 1 and write the contents of the address register and the program code.
By incrementing or decrementing the program counter 4 by 1- while comparing the contents of the new counter 4 and stopping the block counter 4 when the two match, 1) MA (die reflex 1- memory access) Data transfer can also be performed.

[Example 2] Next, other embodiments of the present invention will be described.

In this embodiment, for example, a single-chip microcomputer package is provided with an external terminal for mode setting. And R
During AM testing, when an appropriate control signal is applied to this external terminal for mode setting, a predetermined mode is set within the single-chip microcontroller.
The I'U and RAM are separated.

Also, when set to dest mode, single-chip
The internal address bus in the microcomputer is connected to the test 1 through the external address bus and the external data bus connected to the output capo-1, along with the internal data bus. 1 Therefore, when nQ is set to the test mode, the single-chip microcontroller appears from the outside as if it were a J(AM), and by inputting 71~res from the Nast device, the internal RAM becomes CPtJ. You can access it directly without going through it.

As a result, the conventional CP u Q7. The built-in I (8M) was tested using a Nast device (logic tester) for (1: 11) By separating U and RAM, it became a test device (memory tester) dedicated to 1<ΔM. Single chip by
It becomes possible to test the RAM inside the microcomputer.

Therefore, the test 1 device 15 for RAM has a pattern generator etc. inside and is inexpensive. Therefore, using the test I-' device for RAM, the built-in R, A
If testing of M can be performed, there are advantages in that the testing itself becomes simple, the creation of a Nast pattern becomes easy, and loss-down becomes possible.

In addition, the difference in the use of external terminals for mode setting is due to CI
) Directly read data by accessing I(AM) in the Shintal chip microcontroller from the outside without going through tJ.
) A new feature is added that allows you to add data.

[Effects] (1) The data processing device 1 with built-in R and AM can directly transfer data from the input/output board to the middle of the internal bus.
A switching circuit is provided to enable data to be transferred directly to the input/output port, or directly from the T (AM) to the input/output port. Since the structure is configured so that data can be transferred directly from RAM to output capo-1 or conversely from input/output capo-1 to RAM, a 1-by-1- death pattern can be written to and read from RA and M in each cycle. As a result, the testing time for the built-in RAM and internal registers can be significantly shortened, and the creation of a dead pattern can also be facilitated.

(2) Data from the input/output capo "-1" is directly converted to 1 by ΔM in the middle of the internal bus in the data processing device with built-in RAM.
A switching circuit is provided to allow data to be transferred directly from RAM to input/output port 1 or directly from RAM to input/output port, so by simply switching the switching circuit in advance, data can be transferred directly from RAM to input/output port 1 or vice versa. RAM from capo-1
Due to the effect of being able to transfer data to C.
I) By combining with the Haas I-instruction, which reads data directly from memory without going through the U, and address registers, we have introduced a new function that allows you to easily perform data chores such as DMA transfer. There is an effect that it can be done.

(3) In a single-chip microcontroller with built-in RAM, an external terminal is provided for setting the worst mode, and when the worst mode is set, the built-in RAM is disconnected from the CI, etc., so that the internal data can be directly accessed from the outside. R.A.
The built-in RAM M can be accessed using the memory test I-device.
This allows for testing of
This has the effect of making RAM testing easier.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, single chip
The configuration of the microcomputer and internal switching circuit is not limited to that of the embodiment described above, and various modifications can be considered.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to single-chip microcontrollers, which is the field of application that formed the background of the invention, but the invention is not limited to this, and the invention is not limited to that. This is a data processing circuit device that can be used in general.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a single-chip microcomputer. 1...CI)U (microprocessor), 2...
...Iku0M (read-only memory), 3...
I (ΔM (random access memory, memory that can be written and read at any time), 4...program counter,
5...Timer, 6...I/O capo-I~, 7...
...Serial 110.8...Internal lotus, 9...
External bus, ]0...Test equipment 1q, 11...
Switching circuit, M, PtJ...Single chip microcomputer.

Claims (1)

[Claims] (1) A data processing device having a memory inside a semiconductor chip, characterized in that the memory is separated from other circuits in a specific state and can be accessed directly from the outside. data processing equipment. 2゜If the memory described in item 1 is a memory that can be written to and read out at any time, and this memory and other circuits are connected by an internal bus, the internal bus has a function for switching the data transfer direction. A switching circuit is provided, and under certain conditions, the built-in memory is connected to an external bus via an internal bus, so that data can be transferred directly to and from an external device. A data processing device according to claim 1, characterized in that: 3. An external terminal for mode setting is provided, and the built-in memory is set to the specific state by a control signal supplied to the external terminal, and is separated from other circuits so that it can be accessed directly from the outside. A data processing device according to claim 1, characterized in that: