JPS605539U - Multiprocessor communication device - Google Patents

Multiprocessor communication device

Info

Publication number
JPS605539U
JPS605539U JP9661583U JP9661583U JPS605539U JP S605539 U JPS605539 U JP S605539U JP 9661583 U JP9661583 U JP 9661583U JP 9661583 U JP9661583 U JP 9661583U JP S605539 U JPS605539 U JP S605539U
Authority
JP
Japan
Prior art keywords
processors
communication device
communication
multiprocessor communication
status
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9661583U
Other languages
Japanese (ja)
Inventor
明 伊藤
松丸　宏
Original Assignee
株式会社日立製作所
日立産機エンジニアリング株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所, 日立産機エンジニアリング株式会社 filed Critical 株式会社日立製作所
Priority to JP9661583U priority Critical patent/JPS605539U/en
Publication of JPS605539U publication Critical patent/JPS605539U/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本考案の一実施例を示す構成図、第２図は、
第１図の部分詳細図である。 １・・・・・・通信状態表示装置、２・・・・・・ラッ
チメモリ、Ｐ□〜Ｐｎ・・・・・・プロセッサ、Ｓ□〜
Ｓｎ・・・・・・通信状態表示バス、ＳＷ・・・・・・
通信状態書込み線、Ｒ４−Ｒｎ・・・・・・読出し出力
線。FIG. 1 is a configuration diagram showing an embodiment of the present invention, and FIG.
FIG. 2 is a detailed view of a portion of FIG. 1; 1...Communication status display device, 2...Latch memory, P□~Pn...Processor, S□~
Sn...Communication status display bus, SW...
Communication status write line, R4-Rn...Read output line.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] マルチプロセッサシステムにおいて、プロセッサ複数台
と、これらプロセッサ間を相互に結ぶ通信インターフェ
ースを持つシステムに於いて、前記各プロセッサの通信
状態、負荷状態を、相互に読み書きできる共通記憶領域
を用い、前記プロセッサの相互監視により、前記プロセ
ッサの処理状態に応じた通信制御をする装置を設けたこ
とを特徴とするマルチプロセッサ間通信装置。In a multiprocessor system that has multiple processors and a communication interface that interconnects these processors, the communication status and load status of each of the processors can be stored using a common storage area that can be read and written to each other. 1. A multi-processor communication device comprising: a device for controlling communication according to processing states of the processors through mutual monitoring.
JP9661583U 1983-06-24 1983-06-24 Multiprocessor communication device Pending JPS605539U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9661583U JPS605539U (en) 1983-06-24 1983-06-24 Multiprocessor communication device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9661583U JPS605539U (en) 1983-06-24 1983-06-24 Multiprocessor communication device

Publications (1)

Publication Number Publication Date
JPS605539U true JPS605539U (en) 1985-01-16

Family

ID=30230176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9661583U Pending JPS605539U (en) 1983-06-24 1983-06-24 Multiprocessor communication device

Country Status (1)

Country Link
JP (1) JPS605539U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62162316A (en) * 1986-01-11 1987-07-18 Rohm Co Ltd Magnetic field conducting apparatus
JPS6327010U (en) * 1986-08-07 1988-02-22

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62162316A (en) * 1986-01-11 1987-07-18 Rohm Co Ltd Magnetic field conducting apparatus
JPS6327010U (en) * 1986-08-07 1988-02-22

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