JPH0283900A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the efficiency of a comparing action by directly comparing the prescribed data for comparison inputted from an external part and the data read from a memory cell, deciding the coincidence and non-coincidence of data and outputting it to a chip external part. CONSTITUTION:A memory cell array (a) can write or read the address designated data. The prescribed data for comparison inputted form an external part to a data input terminal (b) for comparison are inputted to a deciding means (c), directly compared with the data read from a memory cell (a) and the coincidence and non-coincidence of data are decided. The decided result is sent to an output means (d) and outputted from the output means (d) to the chip external part. Thus, the efficiency of the comparing action can be improved.

Description

[Detailed description of the invention] Industrial application field Prior art (Figures 9 to 11) Problems to be solved by the invention Means for solving the problems (Figure 1) Example of operation One embodiment of the present invention (Figures 2 to 8) Effects of the Invention [Summary] Regarding a semiconductor memory device, the present invention aims to improve the efficiency of a comparison operation that compares data read from a memory cell array with predetermined comparison data. a memory cell array into which data can be written or read; a comparison data input terminal into which predetermined comparison data is input from the outside; The device is configured to include a determining means for directly comparing data to determine whether data match/mismatch, and an output means for outputting an output signal from the determining means to the outside of the chip.

[Industrial application field]

The present invention (3) relates to a semiconductor memory device used as a frame buffer memory element of an image processing system, and particularly relates to a semiconductor memory device used as a frame buffer memory element of an image processing system, and in particular, data accumulated in a selected memory cell within the memory element and predetermined comparison data input separately from outside the chip. Detects match/mismatch and outputs the result to the outside of the chip.
The present invention relates to a semiconductor memory device having a data comparison function.

In recent years, as image processing systems have become more sophisticated, there has been a tendency for frame buffer storage elements that constitute the systems to be equipped with various additional functions. The data comparison function described above is one such function, and is useful in applications such as changing the color of a specific part of an image constructed in a frame buffer.

[Conventional technology]

FIG. 9 is a diagram showing a main part of a first conventional example of a semiconductor memory device equipped with this kind of function, and is a circuit diagram of a random side I10 buffer of a dual port memory. In FIG. 9, MDQ, -MDQ7 are data input/output terminals, I
B, ~IB are data manual buffers that operate according to the write signal Sw, OB o~OB, data output buffers that operate according to the write signal SR, Go-G, gates that are opened according to the storage control signal ST, R0
~R7 is G. -G, the registers S0 to S7 are data selection/comparison circuits, and the data selection/comparison circuits 30 to S7 are read/comparison control signals (hereinafter referred to as READ/CMP).
At this time, select the data on the terminal A side and display it on the terminal C,
Or, when READ/CMP is a comparison (cMP), terminal A side data and terminal B side data (i.e. R6-R,
, the stored data) and the comparison result (match/
(mismatch) appears on terminal C.

In such a configuration, IBo to IB and I operate according to the I2I Kotatamidate Sw, and the MDQ. ~M
The data input to DQ,l is written into the memory cell.

READ/CMP becomes READ, and the data in the memory cell passes through S0 to So, and then passes through the operating OB and -0Bfi by SR to MDQ.

~MDQ, is output.

Comparison 1) First, operate IB, ~IB, by Sw and M
While taking in the data input to DQ, ~MDQ, , G is sent by ST. -Gn is opened and the captured data is stored in R6-R.

■) Next, set READ/CMP to CMP and transfer the data from the memory cell and the data in R8-R from 30 to S.
The results are output from MDQ, .about.MDQ□ through OB, which is activated by S, l.

FIG. 10 is a diagram showing a second conventional example, in which comparison data from terminal ip is stored in a comparison data storage register Rp via an input buffer, IBp, and this stored data is
- Commonly added to the B terminal of SA. In addition, Section 9.10
In the figure, BM, -BM, are bit mask circuits, and the bit mask circuits BM, -BMfi indicate the MDQ at that time when the bit mask latch signal is at a predetermined logic level.

When the contents of mask registers MR, ~MR,l and mask registers MR, -MRn, which latch the data input to ~MDQ, , as mask data, are °'0, write the relevant bit to the data manual buffer. It is configured with AND gates AND, -AND, and l that disable the signal, and for example, when input data from MDQo is "0",
” and the data from other MDQs, ~MDQ, , is “1”, adding a bit mask latch signal causes the MDQ
, ``0'' is launched only in the mask register MR, of the bit MDQ, and no write signal is applied to the data manual buffer IBo of the bit MDQ.
Writing of (MDQo) is prohibited (ie, masked).

[Problem to be solved by the invention]

However, in such a conventional semiconductor memory device, the process (II) for comparison is executed after the process (I) for storing comparison data is executed. As shown in the timing chart in Figure 11, when the comparison data is frequently changed, it is necessary to execute process (I) each time the data is changed, and this process (1) is a preparatory operation for the actual comparison process. Therefore,
There are problems in that the ratio of preparatory operations increases and the efficiency of the original comparison operations decreases.

Therefore, an object of the present invention is to eliminate the need for the preparation operation corresponding to the above process (I) and improve the efficiency of the comparison operation.

[Means to solve the problem]

FIG. 1 shows a basic block diagram of a semiconductor memory device according to the present invention.

In FIG. 1, there is a memory cell array a that can write data to or read data from a designated cell, and a comparison data input terminal to which predetermined comparison data is input from the outside. a determining means C that directly compares the data for comparison with the data read from the memory cell a to determine whether the data match/mismatch; and an output means that outputs an output signal from the determining means C to the outside of the chip. d.

[Effect]

In the present invention, when comparison data is added to the comparison data input terminal, a comparison operation between the read data from the memory cell array and the comparison data is performed without going through the preparation operation, and the efficiency of the comparison operation is improved. It will be done.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIGS. 2 to 8 are diagrams showing an embodiment of the semiconductor memory device according to the present invention, and are examples in which the semiconductor memory device is applied to a dual port memory having an xn bit configuration.

First, the configuration will be explained. In FIG. 2, 10 is a dual port memory, and the dual port memory 10 includes a random access memory (RAM) and a serial access memory (SAM). RAM is n
A set of I10 buffers 11a to 11n, column decoders 12a to 12n, and sense amplifier/I10 game) 13a
-13n, memory cell arrays 14a to 14n, an address buffer 15 and a row decoder 1.
6, the SAM includes n sets of data registers 17a-1
7n, pointers 18a to 18n, and serial I10 buffers 19a to 19n. Note that 20 is a clock generator, 21 is a refresh address counter, 22 is a serial clock generator, 23 is a read/write control, and 24 is a transfer control.

In addition, C8 is a chip select signal, RAS is a row address strobe signal, CAS is a column address strobe signal, A0 to A or address signal, SC is a serial clock signal, SF is an operation function control signal, and MWE is a bit mask operation and readout signal. /Write control signal, TRG is transfer command/output enable signal, SR is serial output enable signal, M D Qo - M D
Q, is a bit mask data and random data input/output terminal, SDQ, to SDQ, l is a serial data input/output terminal, Ip is a comparison data input terminal, and Vcc and Vss are respective power supplies.

The present invention provides I10 buffers Ila to 11 on the RAM side.
(I), and FIG. 3 is a diagram showing a specific example of the configuration of the I10 buffer. In FIG. 31, a normal read/comparison switching circuit (determination means) 32, and a bit mask circuit 33.

The bit mask circuit 33 has a bit mask latch signal of “H”.
” level, data from MDQO-MDQ (
A mask data storage register 34 that launches the mask data storage register 34 (“1” or “0”), an AND gate 35 that prohibits the passage of a write signal when the data latched in the mask data storage register 34 is “0”, and a read It has an AND gate 36 that prohibits the passage of signals.

FIG. 4 is a circuit diagram of the normal read/comparison switching circuit 32. The normal read/comparison switching circuit 32 converts the read data from the memory cell and the comparison data (denoted by Ip, which is the same as the terminal code for convenience). ENOR gate 3 outputs L” level when both data do not match as a result of direct comparison.
7, and an AND gate 38 that passes the read signal and turns on the transistor T1 when the normal read/comparison control signal is at "L" level (normal read instruction);
Normally, when the read/comparison control signal is at the "H" level (comparison instruction), the AND gate 39 passes the read signal and turns on the transistor T2.

Next, the operation of the entire memory will be explained with reference to the timing chart of FIG. A row address is taken in at the fall of RAS, and a column address is taken in at the fall of CAS, and memory cells in each of memory cell arrays 148-14n are selected in accordance with these addresses. Also, MWE, TRG, S at the falling edge of RAS
Depending on the level of F, the following six modes are selected in appropriate combination.

1) When MWE is at "H" level at the falling edge of RAS, normal read' write mode; U) When MWE is at L level at the falling edge of RAS, bit mask mode; When TRG is "H" level at the falling edge, the RAM side and SAM side are operated independently.IV) When TRG is "L" and the level is "L" at the falling edge of RAS, the RAM side and SAM side are operated independently. V) Comparison mode when SF is high at the falling edge of RAS; Normal read mode when SF is low at the falling edge of Vll) RAS , is.

Now, as shown in the timing chart in Figure 5, MWE=”
L'', TRG="H", SF="H", bit mask mode (II), independent operation cycle mode (■), and data comparison mode (V) are selected. Therefore, I10 buffer In Ila to Iln, first,
Immediately after the fall of RAS, the data input to MDQo to MDQll is taken in as mask data, and after storing this in the mask data storage register 34 for each bit, the comparison data from terminal 1p is taken. It's crowded. here,
In this embodiment, the terminal rp is shared with the C3 (chip select) terminal. In general, dual-port memory does not have a C8 terminal, and the chip is normally specified by the R signal, but it is easier to use if it is provided with a CS terminal, as with other semiconductor integrated circuit devices. It becomes desirable. Also, even if a C8 terminal is provided, dual port memory often has an N C (N OConne
ct) terminal, so if you use this NC terminal, you will not have to increase the number of terminals. The use of the C8/Ip terminal may be switched by time division. In other words, C at the falling edge of RAS
3/Ip terminal is used as a chip select terminal, and C
The C5/Ip terminal at the falling edge of the AS signal may be used as a comparison data terminal.

The comparison data is added to the ■/○ buffers Ila to 11n, respectively, and these I10 buffers 11. In the normal read/comparison switching circuit 32 in a to 11n, the data is directly compared with the data of the memory cell read at that time. As a result of the comparison in the normal read/comparison switching circuit 32, if they match, the normal read/comparison switching circuit 32 outputs an "H" level, and if they do not match, it outputs an "L" level. These match/mismatch data are outputted from MDQO-MDQ to an external data bus (not shown) via the data output buffer 31. In addition, MD in comparison mode
Q0 to MDQIl are 0PEN-DRAI as described later.
N operation, and when the match/mismatch data is at the "■]" level, it is set to H4-Z (high impedance). For example, when a CPU connected to an external data bus receives match/mismatch data (match: high impedance, mismatch: "L" level), it refers to this data and, for example, creates new bit mask data for the next cycle. Execute appropriate processing such as generation.

In this way, in this embodiment, comparison processing can be performed continuously every cycle by simply setting MWE, TRC, and SF to predetermined levels and adding comparison data to the common terminal of C3/rp. can.

In other words, since the operation of storing comparison data as in the conventional example can be omitted, even when changing comparison data frequently, only the comparison processing as shown in Fig. 6 needs to be executed.
The efficiency of the comparison operation can be improved to almost 100%, and the time required for the comparison operation can be shortened.

As an example, consider an image system in which four planes are configured by four semiconductor storage devices #1 to #4, and each plane is connected to a CPU in series on an external data bus in one parallel manner. (See Figure 7). Such a configuration example is often seen in an image system with a large number of display pixels, a multi-level image system, and the like. This configuration is preferable because even if the number of planes increases, the number of bits of the data bus does not need to be increased. For example, each of the four planes corresponds to red, green, blue, and gradation information in the case of a color image, or corresponds to each of four levels of gradation information in the case of a monochrome image. The CPU selectively designates each C3 of #1 to #4, exchanges data with each RAM, and constructs necessary image information on the RAM. Here, when comparing the constructed data with predetermined comparison data from the CPU, the comparison data is transferred to the four planes at the same time, and the results (match/mismatch) are received by the CPU at the same time. It's more efficient to do so. However, the four planes are connected in parallel to the external data bus, and the connection points are wired-OR, so each plane output section is TRl.
-3TATE ()right state), there is a problem that the outputs from each plane collide (fight). As a countermeasure for this, set the output section of each plane to 0PEN-D.
RAIN (open drain) may be used.

FIG. 8 is an example of this countermeasure, and is a circuit diagram of the data output buffer 31 in FIG. 3. In FIG. 8, the data output buffer 31 receives match/mismatch data (“H” for match, “L” for mismatch) or normal read data from the read/comparison switching circuit 32, and converts the data to the normal read data. Same logic signal S and inverted logic signal S2
When S2 is “H” (mismatch or read data “L”), transistor T is turned on to output DQ i (i: 0.I, --・n
) to the "L" level and the AND gate 101 and S+
If the control signal S is "H"("L") when S is "H" (coincidence or read data "H"), transistor T4 is turned on and DQi is set to H" (Vcc
) level, and an output mode register 103. For example, the output mode register 103 operates in response to an output mode register load control signal generated inside the chip during a comparison mode, and during that operation, TRl-3TATE10P input in a time-sharing manner using an address input terminal, for example.
Launch ENDRA IN data. When this latch data is 1", TRI-3TATE is specified, and '
0", 0PEN-DRAIN is specified. In other words, if the data latched in the output mode register 103 is "0", S3 becomes L, and the AND gate 10
As a result of T4 being turned off by 2, T is 0PEN-D
The RA IN state is set, and the above-described data collision can be avoided.

〔Effect of the invention〕

According to the present invention, when comparing data in a memory cell and predetermined comparison data, only the comparison operation can be performed without the need for the preparatory operation corresponding to the above-mentioned process (I). Efficiency can be improved.

FIG. 10 is a block diagram of the I10 buffer showing the second conventional example, and FIG. 11 is a diagram showing the cycle-by-cycle storage and comparison operations common to the first and second conventional examples.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIGS. 2 to 8 are diagrams showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is an overall configuration diagram thereof, and FIG. Fig. 4 is a block diagram of the normal read/comparison switching circuit, Fig. 5 is its timing chart, Fig. 6 is a diagram showing the comparison operation for each cycle, and Fig. 7 is the four planes. FIG. 8 is a configuration diagram of the data output buffer sofa, FIG. 9 is a configuration diagram of the I10 buffer showing the first conventional example, 14a to 14n...Memory cell array, 31・
...Data output cover sofa (output means), 32...
...Normal read/comparison switching circuit (judgment means), Ip
...Data input terminal for comparison.

Claims (1)

[Scope of Claims] A memory cell array (a) capable of writing or reading data into addressed cells; and a comparison data input terminal (b) into which predetermined comparison data is externally input. ), a determining means (c) that directly compares the predetermined comparison data and the data read from the memory cell (a) to determine whether the data match/mismatch, and from the determining means (c) A semiconductor memory device comprising: output means (d) for outputting an output signal of the above to the outside of the chip.