KR100781983B1 - Multi-path accessible semiconductor memory device having check information serving function - Google Patents

Abstract

A multi-path accessible semiconductor memory device having check information serving function is provided to prevent or minimize over-writing of a mail box. A semiconductor memory device comprises a shared memory region and an interface. The shared memory region has a data access path with one of ports installed independently in correspondence to the number of a plurality of processors, and is selectively accessed by the plurality of processors, and is allocated in a memory cell array. The interface has a semaphore region, mail box regions and check regions accessed in correspondence to a specific address of the shared memory region in order to provide interface function during communication among the plurality of processors.

Description

Multi-path accessible semiconductor memory device having a check information serving function

1 is a block diagram of a typical multiprocessor system employed in a portable communication device,

2 is a block diagram of a multiprocessor system employing a memory according to the present invention;

3 is a block diagram illustrating a memory array portion of a multiprocessor system according to the prior art;

4 is a block diagram of a multiprocessor system with multipath accessible DRAM according to one embodiment of the invention,

FIG. 5 is a block diagram illustrating an arrangement relationship between memory areas, ports, and an internal buffer of the DRAM of FIG. 4;

FIG. 6 is a block diagram illustrating an example of an interface operation for a mailbox and a check region between the processors of FIG. 4.

7 is a block diagram of a multiprocessor system with multipath accessible DRAM according to another embodiment of the invention,

8 is a block diagram illustrating an example of an interface operation for providing mailbox check information between processors of FIG. 7;

9 illustrates the operation timing diagrams of FIGS. 4 and 7.

The present invention relates to a multipath accessible semiconductor memory device having a host interfacing function between processors, and more particularly, to a multipath accessible semiconductor memory device having a check information providing function.

In general, a semiconductor memory device having a plurality of access ports is called a multiport memory, and in particular, a memory device having two access ports is called a dual port memory. A typical dual port memory is well known in the art and is a video memory for image processing having a RAM port accessible in a random sequence and a SAM port accessible only in a serial sequence.

On the other hand, although it will be more clearly distinguished from the description of the present invention to be described later, unlike the configuration of such a video memory, the shared memory region of the memory cell array having no SAM port and consisting of DRAM cells read or write through a plurality of access ports In order to thoroughly distinguish the dynamic random access memory from the multiport memory, the present invention will be referred to as a multipath accessible semiconductor memory device in the present invention.

In line with the ubiquitous orientation of human life today, the electronic systems that humans deal with are developing remarkably. Recently, in electronic devices such as portable multimedia systems such as portable multimedia players, handheld phones, or PDAs, manufacturers have adopted a plurality of processors as shown in FIG. 1 to speed up and facilitate performance and operation. A multiprocessor system has been implemented.

Referring to FIG. 1, the first processor 10 and the second processor 12 are connected to each other through a connection line L10, and the NOR memory 14 and the DRAM 16 are configured buses B1-B3. ) And the DRAM 18 and the NAND memory 20 are busted to the second processor 12 through the set buses B4-B6. Here, the first processor 10 may have a modem function for performing modulation and demodulation of a communication signal, and the second processor 12 may have an application function for processing communication data, performing games, entertainment, and the like. Can have The NOR memory 14 having the NOR structure of the cell array and the NAND memory 20 having the NAND configuration of the cell array are both nonvolatile memories having transistor memory cells having floating gates, and the power supply is turned off. It is mounted for the storage of data which should not be erased even if it is, for example, the unique code of the portable device and the preservation data, and the DRAMs 16 and 18 function as main memory for data processing of the processor.

However, in the multi-processor system as shown in FIG. 1, since DRAM is allocated to each processor correspondingly and relatively low-speed UART, SPI, and SRAM interfaces are used, data transfer rate is difficult to be secured sufficiently, resulting in size complexity. Memory configuration costs are also burdensome. Accordingly, a scheme for reducing the occupancy size, increasing the data transfer speed, and reducing the number of DRAM memories employed is illustrated in FIG. 2.

Referring to FIG. 2, it is specifically shown that one DRAM 17 is connected to the first and second processors 12 via buses B1 and B2 as compared to the system of FIG. 1. In order to enable each processor to access one DRAM 17 through two paths as in the structure of the multiprocessor system of FIG. 2, two ports may be connected to the buses B1 and B2 correspondingly. Is required. However, conventional DRAM is a memory with a single port, as is well known.

Therefore, due to the structure of the memory bank and the port structure in the multi-processor system as shown in FIG.

Similar to the intention of the inventors to basically implement a memory suitable for a multiprocessor system such as that of FIG. 2, the prior art with the configuration of FIG. 3 in which the shared memory region can be accessed by multiple processors is incorporated. No. US2003 / 0093628, invented by Matter et al. And published in the United States on May 15, 2003.

Referring to FIG. 3, the memory array 35 includes first, second, and third portions, and the first portion 33 of the memory array 35 is connected to the first processor 70 through the port 37. Are accessed only by the second processor 31 through port 38 and the third portion 32 is accessed by both the first and second processors 70 and 80. The multiprocessor system 50 is shown. In this case, the sizes of the first and second portions 33 and 31 of the memory array 35 may be changed depending on the operating load of the first and second processors 70 and 80, and the memory array 35 may be changed. ) Is implemented as a memory type or a disk storage type.

In order to implement the third portion 32 in the memory array 35, which is shared by the first and second processors 70 and 80 in the DRAM structure, some problems must be solved. As one of such challenges, the placement of memory regions and input / output sense amplifiers in the memory array 35 and proper read / write path control techniques for each port are of great importance.

In addition, UART, SPI, or SRAM interfaces have been used for communication between conventional processors, for example, a modem and an application processor (or a multimedia coprocessor). Such an interface has problems such as speed limitation and an increase in pin count. Entails. In particular, in order to provide a smooth implementation of 3D games, video communication, HDPDA, WiBro, etc., data traffic between a modem and a processor must be greatly increased, and thus, a need for a high speed interface between processors is increased.

Therefore, there is a need for a more appropriate solution that can share the shared memory area allocated within a DRAM memory cell array in a multiprocessor system with two or more processors, while eliminating the problem of low speed interfacing outside the memory. In order to solve this problem, the invention for DRAM interfacing is disclosed in Korean Patent Application No. 2006-0071455 filed on July 28, 2006 by the applicant. However, in Korean Patent Application No. 2006-0071455, there is no method for monitoring a message stored in a mailbox by a processor that has sent a message as to whether or not the message has been processed by a counterpart processor. Therefore, a solution for this is needed.

Accordingly, an object of the present invention is to provide a multi-path accessible semiconductor memory device having a check information providing function that can overcome the above-described conventional problems.

Another object of the present invention is to provide a multipath accessible semiconductor memory device having a check information providing function that enables a processor that sends a message to check whether a message of a mailbox for message transfer between ports is processed.

It is still another object of the present invention to provide a multipath accessible semiconductor memory device having a check information providing function that can prevent or minimize overwriting of a mailbox.

According to an embodiment of the present invention for achieving some of the above technical problems, the semiconductor memory device according to the present invention, the data access path with a selected one of the ports installed independently of each other corresponding to the number of a plurality of processors A shared memory region formed with and selectively accessed by the plurality of processors, the at least one shared memory area being allocated in a memory cell array; An interface unit may include a semaphorer area, mailbox areas, and check areas that are alternately accessed corresponding to a specific address of the shared memory area to provide an interface function during communication between the plurality of processors.

The plurality of memory cells arranged in a matrix of rows and columns in the shared memory area may be a DRAM memory cell including one access transistor and a storage capacitor, and the plurality of memory cells of the shared memory area may be accessed when the interface part is accessed by the specific address. All memory cells connected to a specific word line may be disabled.

The interface unit is commonly enabled when a specific row address is applied, and the semaphore area, mailbox areas, and check areas are accessed according to an individually applied column address, and the mailbox areas and the check area are accessed. Each of the ports may be provided as many as the number of the ports.

The mailbox areas store messages such as permission requests, data transfers, and command transmissions to the counterpart processor according to a preset transmission direction, and when a message is stored in the mailbox areas, the message area is stored in the mailbox area. Interrupt signals, which are signals for informing the processor, may be provided. The interrupt signals are enabled when a message is written to the corresponding mailboxes, and is disabled when a message stored in the mailboxes is read by the counterpart processor.

The check areas store information on whether a message stored in the mailboxes is read by the counterpart processor, and the information stored in the check areas is the other processors except the counterpart processor that reads the message stored in the mailbox. Monitoring is possible at.

When the semiconductor memory device has two ports, each of the semaphorer area and the mailbox area may have a 16-bit storage area, and the check areas may each have a 1-bit or 2-bit storage area. The mapper region may have a 4-bit storage region, each of the mailbox regions may have a 32-bit storage region, and the check regions may each have a 1-bit or 2-bit storage region.

In accordance with another embodiment of the present invention for achieving some of the above technical problems, there is provided a shared memory region selectively accessed by a plurality of processors according to the present invention, and having at least one or more shared memory regions allocated in the memory cell array. The semiconductor memory device includes an interface unit having a semaphorer area and a mailbox area that are alternately accessed corresponding to a specific address of the shared memory area to provide an interface function during communication between a plurality of processors. A check signal or register area for providing check information on whether the partner processor has read a message when a message such as a request for authorization, data transfer, and command transmission to the counterpart processor is stored in accordance with a preset transmission direction in the data storage. It is provided.

The check information may be monitored by the other processors except the counterpart processor that read the message stored in the mailbox. When the message is stored in the mailbox areas, the check information may be a signal for notifying the counterpart processor that the message is stored in the mailbox. Interrupt signals may be provided. Also, the interrupt signals are enabled when a message is written to the corresponding mailboxes, and is disabled when a message stored in the mailboxes is read by a counterpart processor, and the check information is in phase with the interrupt signals. Or may have an opposite phase.

According to the above configuration, overwriting of the mailbox is prevented.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, without any other intention than to provide a thorough understanding of the present invention to those skilled in the art. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific embodiments. Other illustrations, known methods, conventional dynamic random access memories and circuits have not been described in detail in order not to obscure the present invention.

4 is a block diagram of a multiprocessor system with multipath accessible DRAM in accordance with one embodiment of the present invention. Referring to the drawings, the portable communication system includes a first processor 10 performing a first setup task, a second processor 12 performing a second setup task, and the first and second processors 10, And a DRAM 17 having memory regions accessed by 20 in a memory cell array. The portable communication system also includes flash memories 101, 102 connected to the first and second processors 10, 12 via respective buses.

Although not limited, the DRAM 17 shown in FIG. 4 has two ports independent of each other. For convenience, if the port A to which the signal INTa is output is a first port, it is connected to the first processor 10 through a general-purpose input / output (GIPO) line. When the port B, from which the signal INTb is output, is referred to as a second port, it is connected to the second processor 12 through a general purpose input / output (GIPO) line. Here, the first processor 10 may have a modem function or a baseband processing function for processing modulation and demodulation of a communication signal as a processing task, and the second processor 12 may process communication data, a game, or a video. It can have application functions for processing of entertainment, entertainment, etc. as processing tasks. If necessary, the second processor 12 may be a multimedia coprocessor.

In addition, the flash memories 101 and 102 are nonvolatile memories in which a cell connection configuration of a memory cell array has a NOR structure or a NAND structure, and a memory transistor has a MOS transistor having a floating gate. The flash memories 101 and 102 are mounted as a memory for storing data, which is not to be erased even when the power is turned off, such as unique codes of the portable device and preserved data.

As shown in FIG. 4, the DRAM 17 having dual ports can be used to store instructions and data that can be executed on the processors 10, 12. In addition, the DRAM 17 is responsible for the interfacing function between the first and second processors 10 and 12. Although more details will be described later, a DRAM interface is used instead of an external interface in the communication between the processors 10 and 12. By utilizing an interface unit in the DRAM having a semaphorer area and a mailbox area, the processors 10 and 12 perform data communication through a common accessible memory area. When host interfacing between processors is provided through memory, a plurality of processors can access the allocated shared memory area at high speed, thereby improving data transfer and processing speed and making the system size compact.

The system of FIG. 4 may be a portable computing device or portable communication device, such as a mobile communication device (eg, cellular phone), a two-way radio communication system, a one-way pager, a two-way pager, a personal communication system, or a portable computer. It should be understood that the scope and application of the present invention is not limited thereto.

In the system of FIG. 4, the number of processors may be extended to three or more. The processor of the system may be a microprocessor, a CPU, a digital signal processor, a microcontroller, a reduced instruction set computer, a complex instruction set computer, or the like. However, it should be understood that the scope of the present invention is not limited by the number of processors in the system. In addition, the scope of the present invention is not limited to any particular combination of processors when the processors become identical or different.

From now on, the arrangement of the interface unit and the shared memory area in the DRAM 17 of FIG. 4 and the details of the data communication operation between the processors are intended to help the understanding of the present invention with reference to the drawings showing an internal part of the memory device. Only will be explained.

FIG. 5 is a block diagram illustrating an arrangement relationship between memory regions, ports, and an internal buffer of the multipath accessible DRAM of FIG. 4.

In the drawing, four memory regions B1-B4 are disposed in the memory cell array. First, the A bank memory area B1 is accessed by the first processor 10 through the first port A, and the C and D bank memory areas B3 and B4 are accessed through the second port B. It is accessed by two processors 12, and the B bank memory area B2 is accessed by both the first and second processors 10 and 12 through the first and second ports A and B. As a result, the B bank memory area B2 is a shared memory area, and the A, C, and D bank memory areas B1, B3, and B4 are dedicated memory areas accessed only by a corresponding processor. Each of the four memory areas B1-B4 may be configured in bank units of a DRAM, and one bank may have, for example, memory storage of 64MB, 128MB, 256MB, 512MB, or 1024MB.

As shown in FIG. 5, in order to provide an interface between processes through the DRAM, an interface unit such as a register or a buffer is provided inside the DRAM. The interface section has semaphore and mailbox box areas of concept familiar to processing system developers. Here, a specific row address (1FFF800h to 1FFFFFFh, 2KB size = 1 row size) that enables any one row of the shared memory area in the DRAM is variably assigned to the internal register as the interface unit. Accordingly, when the specific row addresses 1FFF800h to 1FFFFFFh are applied, the corresponding specific word line of the shared memory area is disabled, and the interface addition is enabled instead. As a result, the system uses a direct address mapping method to access the semapper area and the mailbox area of the interface unit, and internally interprets a command to access the disabled address to a register inside the DRAM. To do the mapping. Therefore, the chipset's memory controller generates this command in the same way as a cell in other memory, which can prevent precharge miss problems that can be caused by controllers using open parish. do.

In one embodiment of the present invention, the interface area further includes a check area. The check area is an area for storing check information of contents that enable the counter processor to know whether the message is read when the message to the counter processor is stored in the mailbox area.

In FIG. 5, a semaphore area allocated as 4 bits in the internal register, a mail box A to B area allocated as 32 bits, a mail box B to A area allocated as 32 bits, and check A allocated as 1 bit The to B area, the check B to A area allocated as 1 bit, and the spare area Rvd are commonly enabled by the specific row address, and are individually accessed (mapped) according to the applied column address. Here, the check A to B area and the check B to A area may be allocated to 2 bits, 1 bit may store information, and the remaining 1 bit may be used as a spare area. As another example, each of the semaphore area, mail box A to B area, and mail box B to A area may be allocated as 16 bits.

As a result, when the specific row addresses 1FFF800h to 1FFFFFFh are applied, the corresponding partial area A2 of the shared memory area is disabled, and instead the registers in the DRAM are enabled, providing a DRAM interface to the processors. do. The mail box A to B area can be read and written in the first processor 10, but can only be read in the second processor 12 and the write operation is prohibited. In the second processor 12, read and write are possible, but in the first processor 10, only read and write operations are prohibited.

In the semaphore area allocated to the register, control authority for the shared memory area is displayed, and in the mailbox area, a message (permission request, data transfer, command transmission, etc.) to the counterpart processor according to a preset transmission direction is displayed. Is written. In particular, the mailbox write command is used to deliver a message to the counterpart processor via the mailbox area. When the write command is generated, the DRAM generates interrupt signals INTa and INTb as output signals to execute the interrupt processing service of the corresponding processor in a predetermined direction, and the output signals are hardware-oriented GPIOs or UARTs. And so on.

Hereinafter, only a method of delivering a message using mailbox areas in the multi-path accessible semiconductor memory device as described above and a case in which a separate pin is provided for interface operation and check of the check areas will be described. Read or write operations for other shared memory areas and semaphore areas are described in the above-mentioned Korean Patent Application No. 2006-0071455.

6 shows an example of an interface operation for a mailbox and a check region between processors.

As shown in FIG. 6, when the first processor 10 wants to transmit a message such as an authorization request, data transfer, or command transmission to the second processor 12, the message is sent to the mail box A to B area. Write (save). At this time, the DRAM 17 enables (generates) the interrupt signal INTb to notify the second processor 12 that the message is written to the corresponding mailbox, that is, the mail box A to B area.

The interrupt INTb is enabled when a message is written in the mail box A to B area, and is disabled when the second processor 12 reads a message stored in the mail box A to B area.

Thereafter, the first processor 10 monitors the check A to B area and checks whether the second processor 12 reads the message stored in the mail box A to B area. The check register provided in the check A to B area stores information indicating whether or not the message has been read by the second processor 12. The check register provided in the check A to B region may store information having a phase equal to or opposite to that of the interrupt signal INTb.

For example, the operation in the case of having the same phase is as follows. That is, when the interrupt signal INTb is low enabled, when the interrupt signal INTb is low enabled, the second processor 12 does not read the message stored in the mail box A to B area. Since it is not the case, row data (for example, data '0') is stored in the check A to B area. When the interrupt signal INTb is in a high disable state, the second processor 12 reads a message stored in the mail box A to B area, so that high data (for example, in the check A to B area) is read. For example, data '1' is stored. The first processor 10 stores the message in the mail box A to B area and then monitors the check A to B area from time to time to check the information stored in the check A to B area. Checks whether the message stored in the mail box A to B area is read.

When it is confirmed that the message stored in the mail box A to B area is read by the second processor 12, another message is written to the mail box A to B area. By providing the check A to B area as described above, it is possible to prevent a message from being overwritten in the mail box A to B area.

Next, a case in which the second processor 12 intends to transmit a message such as an authorization request, data transfer, or command transfer to the first processor 10. In this case, the second processor 12 writes (stores) a message in the mail box B to A area. At this time, the DRAM 17 enables (generates) an interrupt signal INTa to notify the first processor 10 that a message is written to a corresponding mailbox, that is, a mail box B to A area.

The interrupt INTa is enabled when a message is written to the mail box B to A area, and is disabled when the message stored in the mail box B to A area is read by the first processor 10.

Thereafter, the second processor 12 monitors the check B to A area and checks whether the first processor 10 reads a message stored in the mail box B to A area. The check register provided in the check B to A area stores information indicating whether the message has been read by the first processor 10. The check register provided in the check B to A region may store information having a phase equal to or opposite to that of the interrupt signal INTa.

For example, the operation in the case of having the same phase is as follows. That is, when the interrupt signal INTa is low enabled, when the interrupt signal INTa is low enabled, the first processor 10 does not read the message stored in the mail box B to A area. Since it is not the case, row data (for example, data '0') is stored in the check B to A area. When the interrupt signal INTa is in a high disable state, the first processor 10 reads a message stored in the mail box B to A area. Therefore, high data (for example, in the check B to A area) is read. For example, data '1' is stored. The second processor 12 stores the message in the mail box B to A area and then monitors the check B to A area from time to time to check the information stored in the check B to A area. Checks whether the message stored in the mail box B to A area is read.

When it is confirmed that the message stored in the mail box B to A area is read by the first processor 10, another message is written to the mail box B to A area. By providing the check B to A area as described above, it is possible to prevent a message from being overwritten in the mail box B to A area.

In FIG. 6, only the case of having two processors is described, but the operation or structure in the case of having a plurality of processors may be easily implemented or understood by those skilled in the art. In this case, the check B to A area and the check B to A area can be monitored by other processors except the counterpart processor that read the message.

7 and 8 are related to another embodiment of the present invention, and it is determined whether a message is read from a counterpart processor by adding a separate output pin without having a check area as described with reference to FIGS. 5 and 6. The configuration is shown to be known.

FIG. 7 has a configuration similar to that of FIG. 4 and only the portions having other configurations will be described.

As shown in Fig. 7, the DRAM 17 has two ports independent of each other. For convenience, if the port A, from which the signals INTa and CHb are output, is referred to as a first port, it is connected to the first processor 10 and the second processor 12. The signal INTa input to the first processor 10 functions as an interrupt signal, and the signal CHb input to the second processor 12 is transmitted from the mail box B to the first processor 10. This is a check signal indicating whether or not a message stored in the area A has been read.

When the port B, from which the signals INTb and CHa are output, is referred to as the second port, it is connected to the first processor 10 and the second processor 12. The signal INTb input to the second processor 12 functions as an interrupt signal, and the signal CHa input to the first processor 10 is transmitted from the mail box A to the second processor 12. This check signal indicates whether or not the message stored in the area B has been read.

7 shows whether a message stored in a counterpart processor mailbox area is read using a conventional interrupt signal. This interrupt signal is enabled when a processor writes a message to a mailbox, and is disabled when the counter processor reads a message stored in the mailbox area. In this case, the check signals have the same phase as the interrupt signals. However, the check signals are disabled when interrupt signals are enabled and have an enable state when interrupt signals are disabled.

The operation in this case will be described with reference to FIG. 8 as follows.

First, when the first processor 10 intends to transmit a message such as an authorization request, data transfer, or command transmission to the second processor 12, the message is written (stored) in the mail box A to B area. At this time, in the DRAM 17, the interrupt signal INTb is low enabled (generated) to notify the second processor 12 that the message is written to the corresponding mailbox, that is, the mail box A to B area. In this case, the check signal CHa maintains the disabled state in phase with the interrupt signal INTb.

Subsequently, when the second processor 12 reads the message stored in the mail box A to B area, the interrupt signal INTb is high disabled. At the same time, the check signal CHa is enabled high to inform the first processor 12 that the message stored in the mail box A to B area has been read.

When the first processor 10 confirms through the check signal CHa that the message stored in the mail box A to B area is read by the second processor 12, the mail box A to B area is confirmed. Will write another message.

Next, when the second processor 12 wants to transmit a message such as an authorization request, data transfer, or command transmission to the first processor 10, the message is written (stored) in the mail box B to A area. At this time, in the DRAM 17, an interrupt signal INTA is low enabled (generated) to notify the first processor 10 that a message is written to a corresponding mailbox, that is, a mail box B to A area. In this case, the check signal CHa maintains the disabled state in phase with the interrupt signal INTa.

Subsequently, when the first processor 10 reads a message stored in the mail box B to A area, the interrupt signal INTa is high disabled. At the same time, the check signal CHb is enabled high to inform the second processor 12 that the message stored in the mail box B to A area has been read.

In the second processor 12, when it is confirmed through the check signal CHb that the message stored in the mail box B to A area is read by the first processor 10, the mail box B to A area is determined. Will write another message.

9 illustrates the operation timing diagrams of FIGS. 4 and 7. Although shown in the drawings together for convenience of description, the case where the check register is provided with the check register or the check signal using the interrupt signal is clearly different. That is, it is apparent that the check signal using the interrupt signal is not generated when there is a check register, that is, the check area, and the check register does not exist when the check signal using the interrupt exists.

9 illustrates an example in which a message is stored in a mailbox and read by a second processor 12 in the first processor 10.

As shown in Fig. 9, the first processor 10 checks whether a message can be stored in a mailbox through a check register or a check signal in the check area. In this case, since the check register stores data '1' or the check signal is high enabled, the first processor 10 writes a message to the mailbox. That is, the message of D0 to D3 is stored. Thereafter, the first processor 10 may write the message in the mailbox and continuously monitor the check area or the check signal, or monitor only when the other message is to be delivered.

When the message is stored in the mailbox by the first processor 10, the DRAM transmits the interrupt signal INTb low to the second processor 12. The check register is storing data '0' or the check signal is changed to the low disable state.

Accordingly, the second processor 12 reads the message stored in the mailbox. Since the check information remains in a disabled state or a data '0' state until the second processor 12 reads the message stored in the mailbox, the first processor 10 stores the check information CHa. It is possible to check whether it is possible to write another message to the mailbox.

When the message stored in the mailbox is read by the second processor 12 that the message is stored in the mailbox through the interrupt signal INTb, the interrupt signal INTb is disabled. The check information CHa changes to a data '1' state or a high enable state.

Thereafter, the first processor 10 stores another message in the mailbox through the check information.

By the above-described configuration, the processor which sends the message through the mailbox can know whether the partner processor has read the message, thereby preventing the duplication of the message or overwriting the mailbox.

Although the above description has been given by way of example only with reference to the embodiments of the present invention, it will be apparent to those skilled in the art that the present invention may be variously modified or changed within the scope of the technical idea of the present invention. . For example, in the case of different matters, various modifications or changes may be made to a register configuration or a circuit configuration and an access method in a memory without departing from the technical spirit of the present invention.

For example, one of the four memory areas may be designated as the shared memory area, and the remaining three may be designated as the dedicated memory area, or all four memory areas may be set as the shared memory area. In the case of a system using two processors, the example is mainly used. However, when three or more processors are employed in a system, three or more ports are installed in one DRAM and one of three processors is installed at a specific time. You will be able to access the configured shared memory. In addition, although the DRAM has been exemplified, the technical spirit of the present invention may be extended to a static random access memory or a nonvolatile memory, without being limited thereto.

As described above, according to the present invention, by providing a check register or a separate pin for checking, it is possible to know whether or not the partner processor reads a message stored in a mailbox. Overwriting is prevented.

Claims (17)

In a semiconductor memory device: A shared memory allocated to at least one of the ports installed independently of each other in correspondence with the number of processors is formed and selectively accessed by the plurality of processors, wherein at least one shared memory is allocated in the memory cell array. An area; And an interface unit having semapper areas, mailbox areas, and check areas that are alternately accessed corresponding to a specific address of the shared memory area to provide an interface function during communication between the plurality of processors. A semiconductor memory device. The method of claim 1, And a plurality of memory cells arranged in a matrix of rows and columns in the shared memory area are DRAM memory cells including one access transistor and a storage capacitor. The semiconductor memory device of claim 2, wherein all of the memory cells connected to a specific word line of the shared memory area are disabled when the interface portion is accessed by the specific address. The semiconductor device of claim 3, wherein the interface unit is commonly enabled when a specific row address is applied, and the semaphore area, the mailbox areas, and the check areas are accessed according to individually applied column addresses. Memory device. The semiconductor memory device of claim 4, wherein the mailbox areas and the check areas are provided as many as the number of ports. The semiconductor memory device of claim 5, wherein the mailbox areas store messages such as a request for authorization, a data transfer, and a command transfer to a counterpart processor according to a preset transfer direction. The semiconductor memory device of claim 6, further comprising interrupt signals, which are signals to notify the counterpart processor that the message is stored in the mailbox when the message is stored in the mailbox areas. 8. The semiconductor memory device of claim 7, wherein the interrupt signals are enabled when a message is written to corresponding mailboxes, and disabled when a message stored in the mailboxes is read by a counterpart processor. The semiconductor memory device of claim 8, wherein the check areas store information about whether a message stored in the mailboxes is read by a counterpart processor. 10. The semiconductor memory device of claim 9, wherein the information stored in the check areas can be monitored by processors other than the counterpart processor that read the message stored in the mailbox. The semiconductor device of claim 10, wherein when the semiconductor memory device has two ports, each of the semaphorer area and the mailbox area each has a 16-bit storage area, and the check areas each have a 1-bit or 2-bit storage area. A semiconductor memory device characterized by having. The semiconductor device of claim 10, wherein when the semiconductor memory device has two ports, the semaphore area has a 4-bit storage area, each of the mailbox areas has a 32-bit storage area, and each of the check areas is 1. A semiconductor memory device having a bit or two bit storage area. A shared memory area selectively accessed by a plurality of processors, the shared memory area being allocated in at least one memory cell array, and corresponding to a specific address of the shared memory area to provide an interface function in communication between the plurality of processors. A semiconductor memory device having an interface portion having a semaphorer area and a mailbox area that are alternately accessed by: A check for providing check information on whether the counterpart processor reads a message when a message such as an authority request, data transfer, and command transmission to the counterpart processor is stored in the mailbox areas according to a preset transmission direction; And a signal or register area. The method of claim 13, And the check information can be monitored by the other processors except the counterpart processor that read the message stored in the mailbox. 15. The semiconductor memory device according to claim 14, wherein when a message is stored in the mailbox areas, interrupt signals, which are signals for informing a counterpart processor that the message has been stored in the mailbox, are provided. The semiconductor memory device of claim 15, wherein the interrupt signals are enabled when a message is written to corresponding mailboxes, and disabled when a message stored in the mailboxes is read by a counterpart processor. The method of claim 16, And the check information has the same phase or the opposite phase to the interrupt signals.

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