JPH06349275A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To increase the number of ports while restraining the hardware resource from increasing, and to allow reduction of dead space in the placement of both cell array regions. CONSTITUTION:The semiconductor memory comprises a three port cell part 208 allowing simultaneous access of three ports and a single port cell part 201 having one access port connected commonly with at least a pair of bit lines b11, b11B. The cell part 201 is placed laterally whereas the cell part 208 is placed longitudinally so that the long side of the region placing the smaller single port cell part opposes the short side of the region placing the larger three port cell part. Most preferably, the long side of the single port cell placing region has same dimension as the short side of three port cell part placing region. The number of ports to be mixed may be determined arbitrarily. A cell part having more than three types of port may also be mixed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a data RAM used in an information processing device such as a DSP (Digital Signal Processor).

[0002]

2. Description of the Related Art Conventionally, a multi-port RAM capable of being simultaneously accessed by a plurality of addresses is known.

FIG. 4 shows an example thereof. 401
Is a data RAM having multiple ports, 402, 40
Reference numeral 3 is a register for holding read data from the RAM 401, 404 is an ALU for performing arithmetic processing based on the data held in the registers 402, 403, 405 is a register for holding the operation result of the ALU 404, 406 is a register 405 to the RAM 401. A tri-state buffer that opens and closes a transfer path of write data to and from the CPU, 407 is a CPU that controls these storage device components 401 to 406.
Is.

A case where information processing, for example, pipeline arithmetic processing is performed in this storage device will be described.

First, the CPU 407 makes a read access to the RAM 401 by using two of the independent addresses A1 to A3 of 12 bits, for example, A1 and A2. Then, the read data R1 and R2 from the respective addresses from the RAM 401 are stored in the respective registers 402 and 403. The ALU 404 uses the registers 402,
Perform arithmetic processing based on the data stored in 403,
The result is stored in the register 405. CPU407
When it knows that the data set to the register 405 is completed, it performs write access to the RAM 401 by using at least one of the addresses A1 to A3, for example, A3, and at the same time turns the tri-state buffer 406 into the on state and the RAM 401 The contents of the register 405 are written in. After that, in order to read the data including at least the data written in the previous step, the read access to the RAM 401 is performed using two of the addresses A1 to A3. Pipeline operation processing is achieved by repeating such a cycle. The final result of the pipeline arithmetic processing is sent from the register 405 to the data bus (not shown) through the tri-state buffer 406, or
It is once stored in the RAM 401.

According to this storage device, it is possible to simultaneously access up to three ports. For example, register 4
When the RAM 401 is accessed by the addresses A1 and A2 in order to store the read data R1 and R2 in 02 and 403, the RAM 40 is simultaneously used by using the address A3.
Since it is possible to access 1 and send the read data R3 to the data bus, it is possible to execute high-grade applications.

[0007]

However, depending on the application, there are many cases where only a part of all ports is required. The increase in the number of ports is accompanied by an increase in the number of metal lines such as bit lines and word lines connected to each memory cell, an increase in the pattern area on the chip, and an increase in power consumption. for that reason,
If only some applications fully use the ports, the redundancy of hardware resources will increase, and for economic reasons, the number of ports will be reduced and some of them will require more ports. There is no choice but to sacrifice application execution.

Further, since the memory capacity of the data RAM that can be made on-chip is limited by the pattern area of the data RAM, the required memory capacity may not be secured in some cases.

The present invention has been made in view of the above problems of the prior art. An object of the present invention is to provide a semiconductor memory device capable of increasing the number of ports while suppressing an increase in hardware resources. To provide.

[0010]

A semiconductor memory device of the present invention has an m port cell section having m (positive integer) access ports and n (a positive integer larger than m) access ports. It is characterized by comprising a port cell section and at least one pair of bit lines commonly connected to the m-port cell section and the n-port cell section.

Then, first and second rectangular regions having the same size on at least one side are provided on the semiconductor substrate, and the m port cell portion is formed in the first rectangular region, and n
The port cell portion is preferably formed in the second rectangular area which is laid out so that the sides having the same dimensions as the first rectangular area face each other.

[0012]

According to the present invention, different numbers m
Since there are cell parts each having n and n ports and these are connected by a common bit line, the n port cell part secures the necessary minimum number of ports, and the other parts are configured as m port cell parts. By doing so, it is possible to increase the number of ports while suppressing an increase in hardware resources.

Further, the m-port cell portion and the n-port cell portion are formed on a rectangular region having at least one side having the same size, and the sides having the same size are made to face each other and laid out so that both widths are uniform. It is possible to prevent a dead space from being generated when arranging.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a data RA according to an embodiment of the present invention.
3 shows a schematic configuration of M.

In this figure, 101 is a 1-port cell section that can be accessed by each address, 102 is a 3-port cell section that can be simultaneously accessed by three addresses, 103 is a row decoder, 104 is a column decoder and I / O buffer. , 105 are control units. The 1-port cell unit 101 is composed of words in the lower half of the address area, and the 3-port cell unit 102 is composed of words in the upper half of the address area. The row decoder 103 controls word line selection according to an address, and the column decoder 104
Controls the bit line according to the address, and the control unit 105 has a function of controlling the precharge and read / write enable of the bit line by the control signal C and a function of synchronizing the operation of the RAM with the clock signal CLK. , And has a function of separating the addresses A1 to A3 into row addresses and column addresses and supplying them to the respective decoders 103 and 104. The address A1 is the cell portion 10 of the data RAM
It is possible to access all 1,102 address areas. The addresses A2 and A3 are the cell portion 10 of the data RAM.
It is possible to access only 1, that is, the lower half address area. When this data RAM is used as one port, it is accessed only by the address A1, and the data read / written at this time are read data R1 / write data W. Data RAM is 3
When used as a port, access is made with addresses A1 to A3. At this time, the data read / written are read data R1 to R3 and write data W.

FIG. 2 shows a cell portion 1 of the data RAM shown in FIG.
The configuration of 01 and 102 is shown.

In this figure, the 1-port cell section 101 includes a cell 201, which is a cell inverter 2
02, 203 and nch transistors 204, 205. The common connection point between the input end of the cell inverter 202 and the output end of the cell inverter 203 is connected to one end between the source and drain of the transistor 204 (hereinafter referred to as a signal transmission line), and the other end of the signal transmission line is a bit. Connected to the line bl1, the common connection point between the output end of the cell inverter 202 and the input end of the cell inverter 203 is connected to one end of the signal transmission line of the transistor 205, and the other end of the signal transmission line is connected to the bit line bl1B. Has been done. The gates of these transistors 204 and 205 are connected to the corresponding word lines. In the case shown, it is connected to the word line wl1. 206 and 206 'are nc for precharging the bit lines bl1 and bl1B.
The h-transistor has its gate connected to the precharge signal line pr1.

The 3-port cell unit 102 includes a cell 208, which is composed of cell inverters 209 and 210 and nch transistors 211 to 216 for switching.

The gates of the transistors 211 and 212 are connected to the word line wl2. Cell inverter 209
The common connection point between the input end of the cell inverter 210 and the output end of the cell inverter 210 is connected to one end of the signal transmission path of the transistor 211, and the other end of the signal transmission path is connected to the cell inverter 202,
It is connected to the bit line bl1 common to 203. The common connection point between the output end of the cell inverter 209 and the input end of the cell inverter 210 is connected to one end of the signal transmission line of the transistor 212, and the other end of the signal transmission line is a bit line common to the cell inverters 202 and 203. It is connected to bl1B.

A common connection point between the input terminal of the cell inverter 209 and the output terminal of the cell inverter 210 is connected to the gate of the transistor 213, and the output terminal of the cell inverter 209 and the input terminal of the cell inverter 210 are connected to the gate of the transistor 214. And a common connection point with the signal transmission paths of the transistors 213 and 214 are connected in series with each other. The gate of the transistor 215 is connected to the word line wl4, one end of the signal transmission line of the transistor 215 is connected to the bit line bl2, and the other end is connected to the other end of the signal transmission line of the transistor 213. The gate of the transistor 216 is connected to the word line wl3, one end of the signal transmission path of this transistor 216 is connected to the bit line bl2B, and the other end is connected to the transistor 21.
4 is connected to the other end. Reference numerals 207 and 207 'denote nch transistors for precharging the bit lines bl2 and bl2B, and their gates are precharge signal lines pr2.
It is connected to the.

The read control unit includes a sense amplifier 217 and output buffers 218 to 221. The sense amplifier 217 senses data on the bit lines bl1 and bl1B, and its output is output to the external data bus via the buffer 218. This buffer 218 is composed of a tri-state buffer and has a read enable signal line r.
It is controlled on / off by e. Output buffer 21
Reference numerals 9 and 220 are composed of inverters, and both of them are connected in cascade on a bit line bl2. The output buffer 221 is also composed of an inverter and is connected to the bit line bl2B.

The write control section comprises nch transistors 221 and 222 for write enable / disable control and input buffers 223 and 224. The gates of the transistors 221 and 222 are write enable signal lines w
transistor 221 connected to the bit line bl2.
One end of the signal transmission path of the transistor 222 is connected to the bit line bl2B. The buffers 223 and 224 are configured as inverters, and both are connected in cascade with the buffer 223 as the write data w input end side. The other end of the transistor 221 is connected to the output end of the buffer 224.
The other end of 2 is connected to the common connection point of the buffers 223 and 224.

The data RAM of this embodiment constructed as described above operates as follows.

Precharge signals pr1 and pr2 and word lines wl1 to wl4, re and we are all active "H".
Is. [1] When data is read by using the data RAM as one port The precharge signal pr1 precharges the bit lines bl1 and bl1B. After precharging, the word line wl1 (or wl2) is selected by the address A1 and becomes active.

If the word line wl1 is selected, the transistors 204 and 205 of the cell 201 are turned on, and the non-inverted data and the inverted data of the cell inverters 202 and 203 are sent to the bit lines bl1 and bl1B.
The data is amplified by the sense amplifier 217, and is output from the output terminal r1 as read data forming 1 bit of the read data R1 on condition that the read enable signal line re is "H".

If the word line wl2 is selected, the non-inverted data and inverted data of the transistors 209 and 210 of the cell 208 are sent to the bit lines bl1 and bl1B, and the sense amplifier 217 amplifies the data.
It is output as read data from the output terminal r1 on condition that the read enable signal line re is "H". [2] When data is written using the data RAM as one port The bit lines bl1 and bl1B are precharged by the precharge signal pr1. After precharging, the word line wl1 (or wl2) is selected and activated by the address A1 as in the case of reading.

Further, the write enable signal line we is set to "H", and the write data is input from the input terminal w. Then, the buffers 223 and 224 input the non-inverted data to the bit line bl1 through the transistor 221, and at the same time, the buffer 223 inputs the inverted data to the bit line bl1B.

As an example, when the input to the bit line bl1 is "H" and the input to the bit line bl1B is "L", the bit line bl1 is held at the precharge level, that is, "H", and the bit The level of line bl1B is "L"
Descend to.

If the word line wl1 is selected, the output of the inverter 202 of the cell 201 is "L",
Since the output of the inverter 203 is stable at "H", the cell 201 has "H" toward the bit line bl1 side,
The output state of "L" is written to the B side.

Similarly, when the word line wl2 is selected, "H" is output to the bit line bl1 side and "L" is output to the bit line bl1B side in the cell 208. [3] 1 write using data RAM as 3 ports,
When two reads are performed simultaneously Bit lines bl1 and b with precharge signals pr1 and pr2
Precharge 11b, bl2 and bl2B.

After precharging, the write enable signal line we is set to "H" and the write data is input from the input terminal w. Then, the buffers 223 and 224 cause the non-inverted data to pass through the transistor 221 to the bit line bl1.
To the bit line bl1B by the buffer 223 at the same time. At this time, when the word line wl2 is selected and activated by the address A1, the data on the bit lines bl1 and bl1B is written to the cell 208 selected by wl2.

Similarly, after precharging, addresses A2 and A
When the word lines wl3 and wl4 are selected by 3 and become active, the data of the cell 208 selected by the word lines wl3 and wl4 is output to the bit lines bl2 and bl2B, and the data forming one bit of the read data R2 and R3. Is output from the output terminals r2 and r3.

As described above, according to the present embodiment, the cell portions 201 and 208 having the respective numbers of 1 and 3 which are different from each other are provided, and these are shared by the common bit line bl.
Since 1 and bl1B are connected, the minimum required simultaneous access capacity is ensured in the 3-port cell unit 208, and the others are configured as the 1-port cell unit 201.
It is possible to increase the number of ports while suppressing an increase in hardware resources.

Next, FIG. 3 shows an example of the layout of the cell portions 201 and 208 on the semiconductor substrate.

As is clear from the drawing, the conclusion is that the layout shown in FIG. 3B is desirable.

That is, both the 1-port cell part arrangement region 301 in which the 1-port cell part 201 is formed and the 3-port cell part arrangement region 302 in which the 3-port cell part 208 is formed are both rectangular, but FIG. In the layout shown in (), both areas 301 and 302 are arranged horizontally. Therefore, a dead space corresponding to the product of the difference between the long sides of the cells 201 and 208 and the short side of the cell 201 is formed on the side of the cell portion 201.

Therefore, the longer side of the smaller one-port cell portion arrangement area 301 and the larger three-port cell portion arrangement area 3
The former 301 is horizontally long so that the short side of 02 is opposed to
The latter 302 is arranged vertically. At this time, the long side of the 1-port cell part placement region 301 and the 3-port cell part placement region 30
When the short side of 2 is the same, it is ideal and no dead space occurs as shown in FIG. 3 (b).

Even if the long side of the 1-port cell part arrangement region 301 and the short side of the 3-port cell part arrangement region 302 are not the same, the dead space reduction effect can be obtained.

In the above embodiment, the case where the cell parts of 1 port and 3 ports are mixed is provided, but the number of ports can be arbitrarily determined. Further, the cell parts of two types of ports are not limited to be mixed, and the cell parts having three or more types of ports may be mixed.

Furthermore, by adding a function of changing the address decoding method by an external control signal as a peripheral circuit of the data RAM, it is possible to change the address area allocated as the cell portion of each port number while the data RAM is in use. Is. That is, even if the address areas targeted for simultaneous 3-port access are different between one process and another process, different address values may point to the same location in terms of hardware depending on the state of the external control signal. By changing the decoding method, it is possible to assign different address areas in terms of software as the cell portion of each port number.

[0042]

As described above, according to the present invention, there is provided a cell portion having m and n ports which are respectively different numbers, and these are connected by a common bit line. , The n-port cell section secures the required minimum number of ports, and the rest is configured as the m-port cell section, whereby it is possible to increase the number of ports while suppressing an increase in hardware resources.

Further, by forming the m-port cell portion and the n-port cell portion on a rectangular region having the same size on at least one side, and arranging the sides having the same size so as to face each other and arranging the widths to be the same, both cell array regions are formed. It is possible to prevent a dead space from being generated when arranging.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a data RAM according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a cell portion of the data RAM shown in FIG.

FIG. 3 is an explanatory diagram showing an example layout layout of the cell section shown in FIGS.

FIG. 4 is a block diagram showing a configuration of a conventional multi-port data RAM.

[Explanation of symbols]

101 1-Port Cell Section 102 3-Port Cell Section 103 Row Decoder 104 Column Decoder and I / O Buffer 105 Read / Write Control Section 201 1-Port Cell Section Cell 206, 206 ′, 207, 207 ′ Bit Line Precharge Control Nch Transistor 208 3 Cell of cell part 217 Sense amplifier 218 to 221 Read data output buffer 223, 224 Write data input buffer 301 1 Port cell part arrangement area 302 3 Port cell part arrangement area R1, R2, R3 Read data W Write data A1 1 port access 12-bit address A2, A3 11-bit address for 3-port access bl1, bl1B 1-port, common bit line for 3-port cell part bl2, bl2B Bit line for 3-port cell part pr1, pr2 Pre Charge signal line r1, r2, r3 read data output end re read enable signal line we write enable signal line wl1, wl2, wl3, wl4 word line w write data input end

Claims (3)

[Claims] 1. An m-port cell section having m (positive integer) access ports, an n-port cell section having n (a positive integer smaller than m) access ports, the m-port cell section and the n-port cell. And at least one pair of bit lines commonly connected to the semiconductor memory device. 2. A first rectangular area provided on a semiconductor substrate in which an m port cell portion is formed, and a short side and a long side of the first rectangular area provided on the semiconductor substrate. 2. The semiconductor memory device according to claim 1, further comprising a second rectangular region in which the layout is arranged so as to face each other and an n-port cell portion is formed. 3. The semiconductor memory device according to claim 2, wherein the short side of the first rectangular area and the long side of the second rectangular area have the same size.