JP3076056B2 - Multi-port memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiport memory, and more particularly to a technique particularly effective when used in a multiport memory included in a digital processing device such as a computer. It is.

[Conventional technology]

There is a multi-port memory having a plurality of access ports, and there is a digital processing device such as a computer including the multi-port memory.

In recent years, the processing capacity required for the digital processing device and the like has been increasing, and accordingly, the number of access ports required for the multi-port memory tends to increase. As is well known, in a conventional multi-port memory, a plurality of word lines and data lines corresponding to the number of access ports are provided in a common memory cell, in other words, a plurality of access ports are shared by sharing a memory array. Has been realized. However, when the number of access ports is, for example, four or more, the layout of the memory array becomes complicated, and it becomes difficult to share the layout. To address this, a regular RA with only a single access port
A so-called parallel RA in which a plurality of M (random access memories) are installed and these RAMs are accessed in parallel during a write operation and independently accessed during a read operation.
The M method has been proposed.

A multi-port memory employing the parallel RAM system is described in, for example, Japanese Patent Application Laid-Open No. 62-180852.

[Problems to be solved by the invention]

However, it has been clarified by the inventors of the present invention that the above-described parallel RAM multiport memory has the following problems. That is, in the multi-port memory of the parallel RAM type, since the plurality of RAMs constituting the multi-port memory have only one access port, the write operation and the read operation cannot be performed simultaneously. Also RAM
As the number of circuit elements increases, the number of circuit elements increases, the required layout area of the multi-port memory increases, the signal transmission time in the chip increases, and the access time decreases. As a result, the operation method of a computer or the like including a multi-port memory is restricted, the machine cycle is limited, and the processing capability is reduced.

A first object of the present invention is to provide a multi-port memory capable of simultaneously executing a write operation and a read operation.

A second object of the present invention is to provide a multi-port memory capable of promoting multi-port memory without sacrificing access time and suppressing an increase in required layout area.

A third object of the present invention is to solve the restriction on the operation method of a computer or the like including a multi-port memory and to improve the processing capability.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
A multi-port memory provided in a digital processing device such as a computer is a write-priority r multi-port RAM having one write port and s read ports.
The write ports of these multi-port RAMs are accessed in parallel, and their read ports are independently accessed. When a plurality of write ports are required and, for example, a byte cut-out function of read data is required, the write ports of the r multi-port RAMs are independently accessed, and the read ports are accessed in parallel. An output selection circuit for realizing a byte cutout function is provided in a multiport memory.

(Operation)

According to the above-described means, one write port and r × s can be shared while sharing the memory array within a layout-possible range, in other words, without sacrificing the access time and suppressing an increase in the layout required area. It is possible to efficiently realize a multi-port memory including three read ports or r write ports and s read ports, and capable of simultaneously executing a write operation and a read operation. As a result, it is possible to solve the restriction on the operation method of the computer or the like including the multi-port memory, speed up the machine cycle, and increase the processing capability.

Embodiment 1 FIG. 1 is a block diagram showing an embodiment of a multi-port memory (LSI) to which the present invention is applied. FIG. 2 is a block diagram showing one embodiment of a multi-port RAM (RAM1 to RAM3) constituting the multi-port memory of FIG. 1, and FIG. 3 is a block diagram of the multi-port RAM of FIG. Is a circuit diagram of an embodiment of the memory array MARY and the column switch CSW included in the embodiment. With reference to these figures, an outline of the configuration and operation of the multi-port memory of this embodiment and its features will be described.

The circuit elements shown in FIG. 3 and the circuit elements constituting each block shown in FIGS. 1 and 2 are formed on one semiconductor substrate such as single crystal silicon, although not particularly limited. Further, in the following block diagram of the multiport memory, the multiport RAM (RAM1 to RAM3) is represented by its three access ports, that is, the write port WP and the read ports RPA and RPB. Further, in FIG. 3, a MOSFET (metal oxide semiconductor type field effect transistor) whose channel (back gate) portion is marked with an arrow. In this specification, a MOSFET is a general term for an insulated gate type field effect transistor. ) Is a P-channel type, and is distinguished from an N-channel MOSFET without an arrow.

The multi-port memory of this embodiment is not particularly limited, but is built in a digital processing device such as a computer.
Combined with multiple similar multi-port memories,
For example, a cache memory or a work storage is configured. These multi-port memories are not particularly limited,
It is mounted on a common board and coupled to an internal bus of a computer or the like via a corresponding memory control unit.

In FIG. 1, the multi-port memory of this embodiment is not particularly limited, but includes three multi-port RAMs (RAM1 to RAM) formed as memory macro cells and functionally coupled.
Including 3). These multi-port RAMs include, but are not limited to, write ports WP and read ports RPA and RPA.
Each has three access ports dedicated to PB. Of these, write port WP of each multi-port RAM
Although not particularly limited, a write clock signal serving as a start control signal is output from a memory control unit (not shown).
CW1 and i + 1-bit write address signal AW10 to AW1
i and input data DI1 are commonly supplied. As a result, the write ports WP of the three multi-port RAMs are always accessed in parallel, and write the same input data to the same designated address. These write ports WP constitute one write port WP1 of the multi-port memory.

On the other hand, the read ports RPA and RPB of each multi-port RAM are not particularly limited, but from the memory control unit, the corresponding start control signals, that is, the i + 1-bit read address signals AR10 to AR1i corresponding to the read clock signals CR1 to CR6. Or AR60 to AR6i, respectively. The read data output from each read port is sent to the memory control unit as output data DO1 to DO6. This allows three multiport RAMs
Read ports RPA and RPB are always independently accessed and output different read data from different addresses. These read ports constitute six read ports RP1 to RP6 of each port memory.

Here, a multi-port RAM (RAM) constituting the multi-port memory
Although not particularly limited, each of the RAMs 1 to 3) basically has a memory array MARY and a column switch CSW arranged so as to occupy most of the layout area as shown in FIG. Although not particularly limited, a write address buffer ABW provided for the write port WP, a write X address decoder XDW, a write Y address decoder YDW, a write amplifier WA, and a data input buffer DIB are provided. Read address buffers ABRA, ABRB and read X address decoders XDRA, XDRB
And read Y address decoders YDRA, YDRB, sense amplifiers SAA, SAB, and data output buffers DOBA, DOBB
Is provided.

The memory array MARY of each multi-port RAM is not particularly limited, but as shown in FIG.
WP and m + 1 write word lines WW0-WWm and read word lines WRA0-WRAm and WRB0-WRBm provided corresponding to the read ports RPA and RPB and arranged in parallel in the horizontal direction of FIG. . Similarly, n + 1 write data lines DW0 to DWn and read data lines DRA0 to DRAn are provided corresponding to the write port WP and the read ports RPA and RPB, and are arranged in parallel in the vertical direction in FIG. And DRB0 to DRBn. At the intersections of these word lines and data lines, although not particularly limited, (m + 1) × (n + 1) single-ended memory cells MC are arranged in a grid.

The memory array MARY further includes two dummy data lines DDA and DDB provided corresponding to the read ports RPA and RPB and arranged in the vertical direction in FIG. It has m + 1 dummy cells DC arranged at the intersection with the line.

Each of the memory cells MC constituting the memory array MARY is not particularly limited, but as illustrated in FIG.
A latch formed by cross-connecting a pair of CMOS inverter circuits N4 and N5 has a basic configuration. In this example,
The commonly connected node between the input terminal of the inverter circuit N4 and the output terminal of the inverter circuit N5 is used as the input node of each latch, and the output terminal of the inverter circuit N4 and the inverter circuit
The node to which the input terminals of N5 are commonly connected is set as the output node of each latch. Inverter circuit N4, the output terminal of which is coupled to the input node of each latch, is designed to have a greater driving capability than the other inverter circuit N5. As a result, the write path and the read path for the memory cell MC are separated, and the write operation is stabilized.

The input node of each latch constituting the memory cell MC is not particularly limited, but the row selection control MOSFET Q14
Are coupled to corresponding write data lines DW0 to DWn. Gates of these row selection control MOSFETs Q14 are commonly coupled to corresponding write word lines WW0 to WWm, respectively. As a result, each memory cell MC is set to the selected state by setting the corresponding write word lines WW0 to WWm to the high level, and follows the write signals supplied via the corresponding write data lines DW0 to DWn. Selectively perform the written operation.

On the other hand, the output node of each latch constituting memory cell MC is coupled to the gates of read MOSFETs Q15 and Q17. The sources of these MOSFETs Q15 and Q17 are coupled to the ground potential of the circuit, and the drains are connected to the corresponding read data lines DRA0-DRAn or DRB0-DRBn via the corresponding read row selection control MOSFET Q16 or Q18, respectively. Be combined. The gates of the row selection control MOSFET Q16 are commonly coupled to the corresponding read word lines WRA0 to WRAm, and the gates of the row selection control MOSFET Q18 are commonly coupled to the corresponding read word lines WRB0 to WRBm. As a result, the memory cell MC is set to the selected state when the corresponding read word line WRA0 to WRAm or WRB0 to WRBm is set to the high level, and the read signal corresponding to the data held in the latch is set to the corresponding read data line. DRA0 ~
Output to DRAn or DRB0 to DRBn.

Incidentally, the read operation of the memory cell MC via the read data lines DRA0 to DRAn and DRB0 to DRBn is performed as follows.
It is possible to execute at the same time. However, if these read operations are performed simultaneously with the write operations via the write data lines DW0 to DWn, the read data is not guaranteed. Therefore, the multi-port RAM of this embodiment
Is an address comparison circuit that compares and compares the write address supplied to the write port WP with the read address supplied to the read ports RPA and RPB, as described later.
An ADC is provided, and when these addresses match, the write operation is executed with priority. At this time, the write data, that is, the input data DI is directly transferred to the data output buffers DOBA and DOBB of the read ports RPA and RPB via the data transfer circuit DTC described later, and is used as read data of each read port. Thus, the multi-port RAM of this embodiment is a so-called write-priority type RAM.
It is said.

Each of the dummy cells DC constituting the memory array MARY is not particularly limited, but as illustrated in FIG.
Two sets of N-channel MOSFETs Q19 and Q provided in series between dummy data line DDA or DDB and the ground potential of the circuit.
20 and Q21 and Q22. Among them, MOSFET19 and
Q21 is the read MOSFETs Q15 and Q1 of the memory cell MC.
7, the gate of which has a corresponding inverted precharge signal φpcaB or φpcbB (here, a so-called inverted signal which is normally set to a high level and selectively set to a low level when it is enabled). Is
The signal name is represented by adding B to the end. The same applies hereinafter). These inverted precharge signals are set to a low level when the corresponding read port RPA or RPB of each multi-port RAM is set to a non-selected state, and are selectively set to a high level at a predetermined timing when set to a selected state. . On the other hand, the MOSFETs Q20 and Q22 are
It has a device structure corresponding to ETQ16 and Q18, and its gate is connected to the corresponding read word line WRA0-WRAm or
Commonly coupled to WRB0 to WRBm.

Thereby, the dummy cell DC is set to the selected state by setting the corresponding read word line WRA0 to WRAm or WRB0 to WRBm to the high level, and the corresponding dummy data line DD
A read signal corresponding to the case where the data held in the memory cell MC is logic “0”, that is, the output node of the latch is set to a high level, is output to A or DDB. These read signals are supplied to a dummy common data line CDDA or CDDB
To the sense amplifier SAA or SAB via the memory, and serves as a reference potential for amplifying the read signal of the memory cell MC and determining its level.

As described above, in the multi-port RAM of this embodiment, by sharing the memory array MARY, three access ports, that is, the write port WP and the read port RPA
And RPB, thereby reducing the number of circuit elements per access port and the required layout area.
In the multi-port RAM of this embodiment, the memory array MAR
The memory cells MC constituting Y are of a single-ended type,
Since each word line and data line are formed as a single signal line, simplification of the memory cell and reduction in the number of required signal lines are achieved, thereby further reducing the required layout area of the memory array MARY. Become.

Write word line WW0 constituting memory array MARY
Although not particularly limited, .about.WWm is coupled to the write X address decoder XDW, and is selectively selected.
In addition, read word lines WRA0 to WRAm and WRB0 to WR
Bm is the corresponding read X address decoder XDRA or
The XDRBs are coupled to each other and each of them is alternatively selected.

On the other hand, the write data lines DW0 to DWn that constitute the memory array MARY are not particularly limited, but the column switches CS
It is selectively connected to the write common data line CDW via the corresponding complementary switch MOSFETs Q1 and Q11 of W, and further connected to the write amplifier WA. These complementary switches MO
The gate of the SFET has a write Y address decoder YDW
Supplies the corresponding column selection signals YW0 to YWn or their inverted signals by the inverter circuit N1. As a result, the write data lines DW0 to DWn are selectively connected to the write common data line CDW and the write amplifier WA by the corresponding column selection signals YW0 to YWn being alternately set to the high level. A predetermined write signal is alternatively transmitted to a specified memory cell MC of the memory array MARY.

Further, the read data lines DRA0 to DRAn and DRB0 to DRBn constituting the memory array MARY are not particularly limited, but one of them is coupled to the power supply voltage of the circuit via the corresponding P-channel type precharge MOSFET Q4 or Q5. Is done. On the other hand, the column switch CS
It is selectively connected to the corresponding read common data line CDRA or CDRB via the corresponding complementary switch MOSFET Q2 and Q12 or Q3 and Q13 of W, and further connected to the corresponding sense amplifier SAA or SAB. The above precharge MOSFET Q4
, The inversion timing signal φpcaB is commonly supplied to the gates, and the gate of the precharge MOSFET Q5 is commonly supplied with the inversion timing signal φpcbB. The gates of the complementary switch MOSFETs Q2 and Q12 and Q3 and Q13 have corresponding read Y address decoders YDRA or YD.
From RB, the corresponding column selection signal YRA0 to YRAn or YR
B0 to YRBn are supplied, respectively. In this example,
The power supply voltage of the circuit is not particularly limited, but is a positive power supply voltage such as + 5V.

From these, the read data lines DRAP to DRAn and DRB0 to DRBn are connected to the circuit when the corresponding read port RPA or RPB of the multi-port RAM is in the non-selected state and the inversion timing signal φpcaB or φpcbB is at the low level. Is precharged to a high level such as the power supply voltage of And the corresponding read port RPA of the multiport RAM
Alternatively, when the RPB is set to the selected state and the inverted timing signal φpcaB or φpcbB is set to the high level, the data held in the (n + 1) memory cells MC coupled to the selected read word line WRA0 to WRAm or WRB0 to WRBm. In accordance with the read level. These read levels are
Corresponding complementary switch MOSFETs Q2 and Q12 or Q3 and Q
When 13 is turned on, the read common data line
It is alternatively transmitted to CDRA or CDRB, and is further sense amplifier
It is transmitted to SAA or SAB.

In FIG. 2, a write X address decoder XDW
Although there is no particular limitation, the j + 1-bit internal address signals awx0 to awxj are output from the write address buffer ABW.
And a timing signal φxw is supplied from the timing generation circuit TG. Similarly, although not particularly limited, the read X address decoder XDRA receives the j + 1 bit internal address signal ar from the read address buffer ABRA.
xa0 to arxaj are supplied, and a timing signal φxra is supplied from the timing generation circuit TG. The read X address decoder XDRB has a read address buffer.
J + 1-bit internal address signals arxb0 to arxbj from ABRB
And a timing signal φxrb is supplied from the timing generation circuit TG.

The write X address decoder XDW is selectively activated by the timing signal φxw being set to the high level. In this operation state, the write X address decoder XDW decodes the internal address signals awx0 to awxj and selectively sets the corresponding write word lines WW0 to WWm of the memory array MARY to a high level selection state. Similarly, read X address decoders XDRA and XD
The RB is selectively activated when the corresponding timing signal φxra or φxrb is set to the high level. In this operation state, the read X address decoder XDRA
And XDRB are the corresponding internal address signals arxa0 to arx
aj or arxb0 to arxbj are decoded, and the corresponding read word lines WRA0 to WRAm or WRB0 to
WRBm is alternatively set to a high level selection state.

On the other hand, although there is no particular limitation on the write Y address decoder YDW, the write address buffer ABW
Supplies the internal address signals awy0-awyk of k + 1 bits, and the timing signal φyw from the timing generation circuit TG. Similarly, the read Y address decoder YD
Although there is no particular limitation on the RA, the k + 1-bit internal address signal arya is output from the read address buffer ABRA.
0 to aryak are supplied, and the timing signal φyra is supplied from the timing generation circuit TG. In addition, the read Y address decoder YDRB receives the k + 1-bit internal address signals aryb0 to aryb from the read address buffer ABRB.
bk is supplied, and a timing signal φyrb is supplied from the timing generation circuit TG.

The write Y address decoder YDW is selectively activated when the timing signal φyw is set to a high level. In this operation state, the write Y address decoder YDW decodes the internal address signals awy0 to awyk and selectively sets the corresponding column selection signals YW0 to YWn to a high level. As described above, these column selection signals are output from the corresponding complementary switches M of the column switches CSW.
It is supplied to OSFETs Q1 and Q11, respectively. Similarly, the read Y address decoders YDRA and YDRB are selectively activated when the corresponding timing signal φyra or φyrb is set to a high level. In this operation state, the Y address decoders YDRA and YDRB for reading read the corresponding internal address signals arya0 to aryak or aryb0 to aryb.
rybk is decoded, and the corresponding column selection signals YRA0 to YRAn
Alternatively, each of YRB0 to YRBn is alternatively set to a high level. As described above, the column selection signals YRA0 to YRAn are output from the corresponding complementary switch MOSFETs Q2 and Q12 of the column switch CSW.
, And the column selection signals YRB0 to YRBn are supplied to the corresponding complementary switch MOSFETs Q3 and Q13, respectively.

The write address buffer ABW captures and holds i + 1-bit write address signals AW0 to AWi supplied from a memory control unit (not shown).
Also, based on these write address signals, j + 1
Bit internal address signals awx0-awxj and k + 1-bit internal address signals awy0-awyk. Of these, the internal address signals awx0 to awxj are supplied to the write address decoder XDW, as described above, and the internal address signals a
wy0 to awyk are supplied to the write Y address decoder YDW. It goes without saying that the total number of bits j + k of these internal address signals has a relationship of i = j + k.

Similarly, read address buffers ABRA and ABRB
Are read address signals ARA0 to ARAi or ARB0 to AR of i + 1 bits supplied from the memory control unit.
Capture Bi and retain it. Further, based on these read address signals, a j + 1 bit internal address signal arxa0 to arxaj or arxb0 to arxbj and a k + 1 bit internal address signal arya0 to aryak or aryb0 to ary
Form bk. Of these, the internal address signals arxa0 to arx
aj and arxb0 to arxbj are supplied to the corresponding read X address decoders XDRA and XDRB, respectively, as described above, and the internal address signals arya0 to aryak and aryb0
~ Arybk are the read Y address decoders YDRA and YDR
B respectively.

Write data line DW specified in memory array MARY
Write common data line CD to which 0 to DWn are alternatively connected
W is coupled to the output terminal of the write amplifier WA. The input terminal of the write amplifier WA is coupled to the output terminal of the data input buffer DIB and to the input terminal of the data transfer circuit DTC. The input terminal of the data input buffer DIB is coupled to the data input terminal DI and the data transfer circuit DIB
The first and second output terminals of the DTC are connected to a data output buffer D.
It is coupled to the input terminals of OBA and DOBB, respectively. The write amplifier WA is supplied with a timing signal φw from a timing generation circuit TG, and the data transfer circuit DTC is supplied with internal control signals ama and amb from an address comparison circuit ADC described later. These internal control signals, as described below,
Write address signals AW0 to AWi and read address signals
When ARA0 to ARAn or ARB0 to ARBn match all bits, they are selectively set to the high level.

On the other hand, the read common data line CDRA to which the read data lines DRA0 to DRAn specified in the memory array MARY are selectively connected, and the dummy common data line CDDA to which the dummy data line DDA is selectively connected, It is coupled to the input terminal of the sense amplifier SAA. The output terminal of the sense amplifier SAA is coupled to the input terminal of the data output buffer DOBA, and the output terminal of the data output buffer DOBA is connected to the data output terminal DOBA.
Combined with A. The data output buffer DOBA is supplied with a timing signal φoca from the timing generation circuit TG. Similarly, the read common data line CDRB to which the read data lines DRB0 to DRBn specified in the memory array MARY are selectively connected, and the dummy common data line CDDB to which the dummy data line DDB is selectively connected are , Is coupled to the input terminal of the sense amplifier SAB. The output terminal of this sense amplifier SAB is coupled to the input terminal of the data output buffer DOBB,
The output terminal of the data output buffer DOBB is the data output terminal
Combined with DOB. The data output buffer DOBB is supplied with a timing signal φocb from the timing generation circuit TG. Note that, as described above, the first or second output terminal of the data transfer circuit DTC is commonly coupled to the input terminals of the data output buffers DOBA and DOBB.

When the write port WP of the multi-port RAM is set to the selected state, the data input buffer DIB captures and holds the input data DI supplied from the memory control unit (not shown) via the data input terminal DI. Further, based on the input data DI, predetermined internal input data di is formed and supplied to the write amplifier WA.

Write amplifier WA is write port WP of multi-port RAM
Are set to the selected state, and the timing signal φw is set to the high level, thereby selectively operating. In this operation state, the write amplifier WA operates in the data input buffer DIB.
A predetermined write signal is formed based on the internal input data di supplied from, and is written to the specified memory cell MC of the memory array MARY via the write common data line CDW.

On the other hand, when the corresponding read port RPA or RPB of the multi-port RAM is set to the selected state, the sense amplifiers SAA and SAB are read from the specified memory cell MC of the memory array MARY via the read common data line CDRA or CDRB. The output read signal is amplified and transmitted to the corresponding data output buffer DOBA or DOBB as internal output data doa or dob. At this time, as described above, the sense amplifiers SAA and SAB output the dummy signal output from the dummy cell DC of the memory array MARY via the dummy common data line CDDA or CDDB,
This is a reference potential for the amplification operation.

When the corresponding timing signal φoca or φocb is set to the high level, the data output buffers DOBA and DOBB
The operation state is selectively set. In this operation state, the data output buffers DOBA and DOBB output the internal output data doa or dob output from the corresponding sense amplifier SAA or SAB.
, A predetermined output signal is formed, and transmitted via the corresponding data output terminal DOA or DOB.

The data transfer circuit DTC outputs the write address signals AW0 to AW
i and the read address signals ARA0 to ARAi match, and when the internal control signal ama is set to the high level, the internal input data di output from the data input buffer DIB is output.
To the data output buffer DOBA as the internal output data doa
Communicate directly to At this time, the read operation by the read port RPA is prohibited, and the write operation by the write port WP is executed with priority. Meanwhile, the data transfer circuit
In the DTC, all bits of the write address signals AW0 to AWi and the read address signals ARB0 to ARBi match, and the internal control signal
Data input buffer DIB when amb is high
Internal input data di output from
As b, it is transmitted directly to the data output buffer DOBB. At this time, the read operation by the read port RPB is prohibited, and the write operation by the write port WP is executed with priority.

As described above, the multi-port RAM uses the address comparison circuit ADC
Is provided. The address comparison circuit ADC receives the internal address signals awx0-awxj, awy0 from each address buffer.
~ Awyk and arxa0 ~ arxaj, arya0 ~ aryak and arxb0 ~
arxbj, aryb0 to arybk are supplied.

The address comparison circuit ADC compares these address signals bit by bit. As a result, the internal address signal
awx0-awxj and awy0-awyk, that is, write address signals AW0-AWi and internal address signals arxa0-arxaj and arya0
~ Aryak, that is, when all the read address signals ARA0 to ARAi match, the internal control signal ama is set to the high level, and the internal address signals awx0 to awxj and awy0 to awyk, that is, the write address signals AW0 to AWi and the internal address signal ar
xb0 to arxbj and aryb0 to arybk, that is, when all the read address signals ARB0 to ARBi match, the internal control signal
Set amb to high level. These internal control signals are supplied to the data transfer circuit DTC and also to the timing generation circuit TG.

The timing generation circuit TG includes a write clock signal CW and read clock signals CRA and CRB supplied as a start control signal from the memory cell MC, and an address comparison circuit.
Based on internal control signals ama and amb supplied from ADC,
The above various timing signals are formed and supplied to each circuit of the multi-port RAM.

As described above, the multi-port memory of this embodiment has r multi-port RAMs formed as macro cells, that is, three multi-port RAMs.
(RAM1 to RAM3), and these multi-port RAMs have one write port WP and s, that is, two read ports RPA and RPB. Of these, the write port WP of each multi-port RAM is accessed in parallel with a common address and write data, and the read ports RPA and RPB are independently accessed with different addresses. Therefore, the multiport memory of this embodiment has one write port WP1 and r ×
s, that is, six read ports RP1 to RP6 are provided.
In this embodiment, the three multiport RAMs constituting the multiport memory are all so-called write-priority RAMs, and the memory array MARY is shared by the write port WP and the read ports RPA and RPB. In other words, each multi-port RAM can simultaneously execute the write operation by the write port WP and the read operation by the read ports RPA and RPB, and the number of circuit elements is reduced as far as layout is possible, resulting in high integration. Is done. As a result, the multi-port memory of this embodiment can execute the write operation and the read operation simultaneously without sacrificing the access time and suppressing the increase in the required layout area. As a result, it is possible to solve the restriction on the operation method of the computer or the like including the multi-port memory, speed up the machine cycle, and increase the processing capability.

Embodiment 2 FIG. 4 is a block diagram showing a second embodiment of a multi-port memory to which the present invention is applied. In addition, the fifth
The figure shows a block diagram of a third embodiment of the multiport memory to which the present invention is applied. The multi-port memory of FIG. 4 basically follows the embodiment of FIG. 1, and the multi-port memory of FIG. 5 is a modification of the embodiment of FIG. It is. Further, three multi-port RAMs constituting the multi-port memory of FIGS. 4 and 5
Are all the same as the multi-port RAM of FIG.
Hereinafter, with respect to the multi-port memory of FIG. 4, only the portions different from the embodiment of FIG. 1 will be described, and with respect to the multi-port memory of FIG. 5, only the portions different from the embodiment of FIG. 4 will be described. Add.

In FIG. 4, the multiport memory (LS
I) includes, but is not limited to, r or three multi-port RAMs (RAM1 to RAM3), and these multi-port RAMs
It has one write port WP and s, that is, two read ports RPA and RPB. Of these, each multi-port RAM
A write clock signal CW serving as a start-up control signal is supplied from a memory control unit (not shown) to the write port WP.
1 to CW3, respectively, and further, i + 1-bit write address signals AW10 to AW1i to AW30 to AW3i and 8
Bit input data DI10 to DI17 to DI30 to DI37 are supplied, respectively. As a result, these write ports WP can be independently accessed with different addresses and write data, respectively, and the multi-port memory has r write ports, that is, three write ports WP1 to WP3.

On the other hand, to the read port RPA of each multi-port RAM, a read clock signal CR1 serving as an activation control signal is commonly supplied from the memory control unit, and further, i + 1-bit read address signals AR10 to AR1i are commonly supplied. . The read data of these read ports is output to the memory control unit as output data DO110 to DO117 to DO130 to DO137. Similarly, a read clock signal CR2 serving as a start control signal is commonly supplied to the read port RPB of each multi-port RAM from the memory control unit, and further, an i + 1-bit read address signal AR
20 to AR2i are commonly supplied. The read data of these read ports is output data DO210 to DO217 to DO210.
The signals are output to the memory control unit as 230 to DO237.
As a result, the multiport memory of this embodiment has two read ports RP1 and RP2.

That is, in this embodiment, the arithmetic processing of the computer or the like including the multiport memory is performed in units of 24 bits, that is, 3 bytes, and the writing and reading operations for the multiport memory are also performed in units of 3 bytes. A computer or the like has three sets of internal buses, and through these internal buses, data to be written to the multi-port memory and a total of 6
Byte read data is transmitted. As described above, one write port WP and two read ports RP
A three-port write and read operation is performed by functionally coupling three multi-port RAMs including A and RPB, and sharing the write clock signals CW1 to CW3 and the write address signals AW10 to AW1i to AW30 to AW3i. A multi-port memory capable of handling data and having substantially one write port and two read ports can be effectively realized. Needless to say, each multi-port RAM
Is a write priority type RAM, and three access ports share a memory array MARY. Therefore, the same effects as those of the embodiment of FIG. 1 can be obtained in the multiport memory of this embodiment.

Note that the computer or the like of this embodiment requires a so-called byte cutout function of selecting read data output from the multi-port memory for each byte, for example.
In the case of this embodiment, an output selection circuit for realizing the byte cutout function is provided in the memory control unit.

The multi-port memory of FIG. 5 incorporates output selection circuits OSL1 and OSL2 required for the byte switching function and the like in its chip. Thereby, the skew between bits of the output data of each multi-port RAM is reduced, and the machine cycle of a computer or the like is correspondingly accelerated.

As shown in the above embodiments, the following effects can be obtained by applying the present invention to a multi-port memory provided in a digital processing device such as a computer. That is, (1) a multi-port memory provided in a digital processing device such as a computer is composed of r multi-port RAMs each having one write port and s read ports; By accessing the ports in parallel and independently accessing the read ports, there is an effect that a multi-port memory having one write port and r × s read ports can be efficiently realized.

(2) A multi-port memory provided in a digital processing device such as a computer is composed of r multi-port RAMs having one write port and s read ports, and the write ports of these multi-port RAMs are By independently accessing the respective read ports and accessing the read ports in parallel, there is obtained an effect that a multi-port memory having r write ports and s read ports can be efficiently realized.

(3) According to the above item (2), an effect is obtained that a multi-port memory suitable for a computer or the like that performs arithmetic processing in units of a plurality of bytes can be realized.

(4) In the above items (2) and (3), the output selection circuit necessary for the byte switching function or the like is built in the multiport memory, thereby reducing the skew between bits of the output data of each multiport RAM. Accordingly, the effect is obtained that the machine cycle of a computer or the like including a multiport memory can be correspondingly accelerated.

(5) In the above items (1) to (4), each of the multi-port RAMs constituting the multi-port memory is a write-priority RAM, so that a multi-port memory capable of simultaneously executing a write operation and a read operation. Can be efficiently realized.

(6) According to the above item (5), an effect is obtained that it is possible to solve the restriction on the operation method of a computer or the like including a multi-port memory.

(7) In the above items (1) to (6), each multi-port RA
By sharing the memory array with a plurality of access ports provided in M, the number of circuit elements of the multi-port RAM can be reduced as far as the layout is possible, and the required layout area can be reduced. .

(8) According to the above item (7), the effect of shortening the signal transmission time in the multi-port memory and shortening the access time can be obtained.

(9) According to the above items (1) to (8), an effect is obtained that a machine cycle of a computer or the like including a multi-port memory can be speeded up and its processing capability can be increased.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in FIG. 1, FIG. 4 and FIG. 5, the number of multi-port RAMs constituting the multi-port memory is arbitrary,
The number of access ports provided in the first embodiment is not limited by this embodiment. Various embodiments can be considered for the combination of the write port and the read port provided in each multi-port RAM, and the numbers do not need to be all the same.
The multi-port RAM does not necessarily have to be a write-first type RAM. In this case, it is necessary to provide a control circuit for the write priority processing outside the multi-port RAM. The memory macro cell that constitutes a multi-port memory is
For example, another type of memory such as an EPROM may be used.
In FIG. 2, the multi-port RAM may simultaneously input and output a plurality of bits of storage data. Further, the memory array MARY may be composed of a plurality of memory mats. In FIG. 3, the memory array MARY
Does not need to be a single-ended memory cell. In the memory array MARY, for example, two adjacent columns of memory cells MC can share a write data line or the like. In FIG. 5, the multi-port memory outputs read data of each multi-port RAM to the memory control unit in addition to output signals of the output selection circuits OSL1 and OSL2, that is, output data DO10 to DO17 and DO20 to DO27. You may. In addition, FIG.
The block configuration of the multi-port memory shown in FIGS. 4 and 5, the block configuration of the multi-port RAM shown in FIG. 2, and the specific circuit configuration of the memory array MARY and the column switch CSW shown in FIG. And various combinations of the control signal, the address signal, the power supply voltage, and the like.

In the above description, mainly the case where the invention made by the present inventor is applied to a multiport memory included in a digital processing device such as a computer, which is the background of the application, is not limited thereto. For example, the present invention can be applied to a multiport memory used alone or a similar multiport memory included in various other digital processing devices. The present invention is widely applicable to multi-port memories having a relatively large number of access ports and digital devices including such multi-port memories.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows. That is, a multi-port memory provided in a digital processing device such as a computer is provided with a write-priority type r having one write port and s read ports.
The multi-port RAMs are configured so that write ports of these multi-port RAMs are accessed in parallel and their read ports are independently accessed. When a plurality of write ports are required and, for example, a byte cutout function of read data is required, the above-mentioned r multiports are used.
The write ports of the RAM are independently accessed, the read ports are accessed in parallel, and a read data output selection circuit is provided in the multi-port memory. As a result, while sharing the memory array within the range that can be laid out, in other words, without sacrificing the access time and while suppressing an increase in the layout required area,
A multi-port memory having one write port and r × s read ports or r write ports and s read ports and capable of simultaneously executing a write operation and a read operation can be efficiently realized. as a result,
It is possible to solve a restriction on an arithmetic method of a computer or the like including a multi-port memory, speed up a machine cycle, and increase its processing capability.

[Brief description of the drawings]

FIG. 1 shows a first example of a multi-port memory to which the present invention is applied.
FIG. 2 is a block diagram showing an embodiment of the multi-port memory of FIG. 1;
FIG. 3 is a block diagram showing an embodiment of a RAM, FIG. 3 is a circuit diagram showing an embodiment of a memory array and a column switch included in the multi-port RAM of FIG. 2, and FIG. Second of multi-port memory
FIG. 5 is a block diagram showing an embodiment of the multiport memory according to the present invention;
FIG. 3 is a block diagram showing an embodiment. LSI: Multi-port memory (large-scale integrated circuit device), RAM1
~ RAM3 …… Multi-port RAM (random access memory), W
P, WP1 to WP3 ... Write port, RPA to RPB, RP1 to RP6 ...
... Readout port. MARY …… Memory array, CSW …… Column switch, XDW…
... X address decoder for writing, XDRA to XDRB ... X address decoder for reading, YDW ... Y address decoder for writing, YDRA to YDRB ... Y address decoder for reading, ABW ... Address buffer for writing, ABRA to A
BRB Read address buffer, ADC Address comparator, WA Write amplifier, SAA, SAB Sense amplifier, DIB Data input buffer, DOBA, DOBB Data output buffer, DTC Data transfer Circuit, TG: Timing generation circuit. MC: Single-ended memory cell, DC: Dummy cell, Q1-Q5: P-channel MOSFET, Q11-Q22: N-channel MOSFET, N1-N5: CMOS inverter circuit. OSL1 to OSL2: Output selection circuit.

──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Yoichi Sato 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Ultra-SII Engineering Co., Ltd. (56) References JP-A-62 -188052 (JP, A) JP-A-1-296486 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/41-11/419

Claims (10)

(57) [Claims] 1. A multi-port memory having a plurality of memory macro cells, wherein each of the memory macro cells includes a read port and a write port, and the multi-port memory includes the plurality of memory macro cells. A write operation for accessing each write port of the memory macro cell in parallel with a common address and common write data, a read operation for independently accessing each read port with a different address, the write operation and the read operation, And an operation of executing the operations in parallel. 2. The memory macro cell according to claim 1, wherein each of the memory macro cells further comprises a write priority control circuit for transmitting data of a write port to the read port when the write address signal and the read address signal match. Features multi-port memory. 3. The multiport memory according to claim 1, wherein each of the memory macro cells includes a memory array and a selection circuit for selecting a memory cell. 4. The multi-port memory according to claim 1, wherein each of said memory macro cells has a plurality of read ports. 5. The memory macro cell according to claim 1, wherein each of the memory macro cells includes one write port and s read ports, and the multi-port memory includes r number of the memory macro cells. A multi-port memory comprising one write port and r × s read ports. 6. The memory cell according to claim 1, wherein said memory cell comprises: a latch unit; and a first and a second amplifying MO transistor each having a gate connected to a first input / output node of said latch unit. A first selection control MOS transistor connected to a drain of the first amplification MOS transistor and a first read data line; a drain of the second amplification MOS transistor and a second read data line And a second selection control MOS transistor connected to the first selection control MOS transistor.
And the gate of the second selection control MOS transistor is connected to the second
And a third selection control MOS transistor connected to a second input / output node of the latch means and a write data line. A multi-port memory, wherein a gate of the transistor is connected to a write word line. 7. A multi-port memory having a plurality of memory macro cells, wherein each of the memory macro cells includes a read port and a write port, and wherein the multi-port memory includes the plurality of memory macro cells. A multi-port memory which performs a read operation of accessing each of read ports of a memory macro cell in parallel with a common address and a write operation of independently accessing each of said write ports with different addresses. 8. The multi-port memory according to claim 7, wherein said multi-port memory further comprises an output selection circuit for selectively transmitting read data from said plurality of memory macro cells. 9. The multiport memory according to claim 7, wherein the multiport memory executes the read operation and the write operation in parallel. 10. The memory macro cell according to claim 7, wherein each of the memory macro cells includes a control circuit for giving priority to writing when a write address signal and a read address signal match. And multi-port memory.