JPH0267973A - Operation ensuring circuit of diagnostic circuit - Google Patents

Abstract

PURPOSE:To prevent the inversion of the value of diagnosis-path activating latch and to detect said inversion quickly by providing a diagnosis-path- activating-condition setting circuit. CONSTITUTION:This circuit comprises OR gates 1 and 4, a circuit 2 for setting diagnosis-path activating conditions and latches 3 (31 - 3n) for diagnostic-path activation. Setting signals are applied to terminals S of the latches 3 in accordance with the setting conditions of the circuit 2 in diagnosis. Then the outputs control the clock of a general latch, and a diagnosis paths are formed. The output of the gate 1 is applied to the reset terminal R in the normal operation, and reset is performed. A system resetting signal (a) and a latch resetting signal (b) are applied to the gate 1. The signal (a) is applied as a pulse signal. The signal (b) is applied as '1' all the time so that the value '1' is not changed. Thus the latches 3 are kept in the reset state. Each output of the latches 3 is inputted into an OR gate 4. An error signal is outputted when any one of the latches 3 becomes the set state although the circuit is not in the diagnostic state.

Description

[Detailed Description of the Invention] [Summary] Regarding a diagnostic circuit for testing the normality of operation of a logic circuit installed together with general logic circuits such as integrated circuits, if the diagnostic circuit itself malfunctions and normal operation is affected. The purpose is to provide a means that can detect the occurrence of a fault in the diagnostic circuit as well as prevent the occurrence of a fault in the diagnostic circuit. and a system reset signal as a manual reset signal for the flip-flops for activating the diagnostic path; and means for calculating the logical sum of the outputs of all the flip-flops for activating the diagnostic path. It is configured by providing

[Industrial Application Field] The present invention provides a diagnostic path activation flip-flop that can be set/reset asynchronously with the normal circuits constituting the logic circuits in integrated circuits, etc., which can be set/reset asynchronously, By setting a specific value in the diagnostic path activation flip-flop, the clock of the flip-flop circuit of the normal circuit can be controlled to activate a path between specific flip-flops. The present invention relates to prevention of malfunction of a diagnostic circuit and means for detecting a failure in the diagnostic circuit itself.

[Prior Art] When manufacturing integrated circuits, it is required to test each integrated circuit at the manufacturing stage to prevent defective products from being shipped.

However, in recent years, the degree of integration of integrated circuits has increased, and it is not easy to test them.

Therefore, a diagnostic circuit is provided in the integrated circuit separately from the normal circuit, and arbitrary data can be set or read from flip-flops (hereinafter also referred to as latches) in the logic circuit. By activating a specific path between the two, it is checked whether data is transferred normally or not, and the transfer time is also estimated.

To explain this type of diagnostic circuit further, normally in integrated circuits, etc., when the circuit does not operate normally due to a failure in one of the logic elements in the logic circuit, it is necessary to identify the cause of the problem. As a means for searching, a scan-in/scan-out circuit is provided.

In this method, a gate is provided to configure a test circuit in addition to the circuit that performs normal logic operations. For example, the gate connects each flip-flop in series, and data is transmitted from the first flip-flop. is input, and this is sequentially applied to each 7-lip 7 connected in a column every clock.
By setting arbitrary data in each flip-flop by shifting to 0, and by sequentially reading data from the last flip-flop, it is possible to check the operation and normality of the internal flip-flops. It is.

In addition, as such a test circuit, a circuit is also used that allows arbitrary data to be set in the flip-flop and data to be read by specifying the address of each of the 7 flip-flops and the 70 flip-flops. .

Using such a function, it is also possible to confirm data transfer between specified flip-flops and confirm the transfer time.

For example, in a logic circuit configured as shown in FIG.
When trying to investigate data transfer from flip-flop 50 to flip-flop 51, AND gate 5
6 to 58 must each satisfy the AND condition, and for this purpose, the AND condition of AND gate 59 must satisfy.

In order to satisfy these conditions, flip-flops 52 to 55 must be set to "1".

Therefore, after setting the flip-flops 52 to 55 to "1" by the scan-in operation described above, if the clocks of the flip-flops 52 to 55 are stopped (<CLK), the flip-flops 50 to 55 are set to "1".
10 paths can be activated.

This results in flip-flop 50 and flip-flop 5.
1 can be measured for data transfer between the two.

The clocks of these flip-flops are controlled by setting a specific value in the diagnostic path activation flip-flop.

FIG. 3 is a diagram explaining such a circuit for activating a diagnostic path, in which 60 and 61 are latches for activating a diagnostic path, 62 to 66 are combinational circuits, 67 and 68 are AND circuits,
Reference numerals 69 to 71 represent latches of general logic circuits, 72 a diagnostic path activation circuit, and 73 a general logic circuit.

In the figure, when the diagnostic path activation latch 60 is set to "0" and the internal output of the combinational circuit 62 is "1", "0" is applied to the clock enable terminal of the latch 69, and the latch 69 is activated. The clock is enabled, and on the other hand, when the diagnostic path activation latch 60 is set to "1", the latch 69 is set to the clock inhibited state.

[Problems to be Solved by the Invention] The diagnostic path activation latch as described above must not operate during normal operation and is used only when diagnosing the circuit. When input, the clock becomes enabled and data can be set.

During system operation, the latch of the -JQ logic circuit continues to hold the value that enables the clock.

However, if for some reason the values of these diagnostic path activation latches are reversed, the negative circuit will malfunction, and since it is a fault in the diagnostic circuit, it will be very difficult to find the cause. There was a problem that it was difficult.

In view of such conventional problems, the present invention prevents the value of the diagnostic path activation latch from being easily inverted, and
The object of the present invention is to provide a circuit system that can immediately detect such occurrences.

[Means for Solving the Problems] According to the present invention, the above objects are achieved by the means described in the claims. That is, the present invention provides a diagnostic path activation flip-flop that can be set or reset asynchronously with the normal circuit constituting the logic circuit, and provides a diagnostic path activation flip-flop that can be set or reset asynchronously with the logic circuit. In a diagnostic circuit configured such that by setting a specific value, it is possible to control the clock of the flip-flop circuit of the normal circuit and activate a path between specific flip-flops, it is possible to control the operation of the system. Inside is a signal with a polarity that always resets the flip-flop for activating the diagnostic path, and during circuit diagnostic operation, a signal that is the logical sum of a signal whose polarity is always opposite to this signal and the system reset signal is used for all diagnostics. This is a circuit for guaranteeing the operation of a diagnostic circuit, which is provided with means for supplying as a reset input to a flip-flop for path activation, and means for calculating the logical sum of the outputs of all the flip-flops for diagnostic path activation.

[Operation] In the above means, the diagnostic path activation flip-flop is reset by the system reset signal, and thereafter, by continuing to apply a signal of polarity to reset the flip-flop to the reset terminal of the flip-flop. The reset state will be forced to continue.

Therefore, stable circuit operation can be expected because it is possible to avoid the polarity of the diagnostic path activation flip-flop being reversed unexpectedly due to, for example, induction or pulse noise.

In the unlikely event that the flip-flops for diagnostic path activation become set regardless of human power due to a hardware failure, etc., the circuit that calculates the logical sum of the outputs of all the flip-flops for diagnostic path activation This can be easily detected by the output.

[Embodiment 1] FIG. 1 is a block diagram of an embodiment of the present invention, where l is an OR gate, 2 is a diagnostic path activation condition setting circuit, and 31 to
3n represents a diagnostic path activation latch, and 4 represents an OR gate.

In the figure, during diagnosis, a set signal is applied to the set terminals (S) of the diagnostic path activation latches 31 to 3n according to the conditions set in the diagnostic path activation condition setting circuit 2, and the latches are set. The output clocks the general latches to form the necessary diagnostic paths.

On the other hand, during normal operation, the diagnostic path activation latch 3
1 to 3n are reset by applying the output of OR gate 1 to their reset terminals (R). A system reset signal and a diagnostic path activation latch reset signal are applied to the OR gate 1 as inputs.

Among these signals, the system reset signal is given as a pulse signal, but the latch reset signal for diagnostic path activation is always given as "1" without changing its polarity (°°1" in this case). The diagnostic path activation latches 3. to 3n are forcibly maintained in a reset state.

Further, each output of the diagnostic path activation latches 31 to 3n is manually inputted to the OR gate 4, and even though it is not in the diagnostic state, one of the diagnostic path activation latches 31 to 3n is in the set state. When this occurs, a latch error signal for activating the diagnostic path is output.

[Effects of the Invention] As explained above, according to the present invention, a flip-flop for activating a diagnostic path that can be set or reset asynchronously with the normal circuit constituting the logic circuit is provided. , by setting a specific value in the diagnostic path activation flip-flop, the clock of the flip-flop circuit of the normal circuit can be controlled to activate a path between specific flip-flops. This diagnostic circuit has the advantage that the influence on the general circuit due to malfunction of the flip-flop for activating the diagnostic path can be greatly reduced, and stable operation of the general circuit can be expected.

In addition, malfunctions due to hardware failures in the diagnostic path activation flip-flops can be quickly detected, and systematic countermeasures can be taken quickly and easily, improving the reliability of circuit operation.Advantages There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of a logic circuit, and FIG. 3 is a diagram explaining a diagnostic path activation circuit. 1.4...OR gate, 2...Diagnostic path activation condition setting circuit, 31-3n...Latch for diagnostic path activation

Claims (1)

[Claims] A flip-flop for activating a diagnostic path that can be set or reset asynchronously with the normal circuit constituting the logic circuit is provided, and the flip-flop for activating the diagnostic path By setting a specific value,
In the diagnostic circuit configured to be able to activate a path between specific flip-flops by controlling the clocks of the flip-flop circuits of the normal circuit, the diagnostic path activation flip-flop is always activated during system operation. A signal that is the logical sum of a signal with the opposite polarity to the system reset signal and a signal that always has the opposite polarity during circuit diagnostic operation is used as the reset input of all diagnostic path activation flip-flops. a means of giving as
1. An operation guarantee circuit for a diagnostic circuit, comprising means for calculating the logical sum of outputs of all diagnostic path activation flip-flops.