JPH04236637A - Microprocessor fault detecting circuit - Google Patents

Abstract

PURPOSE:To prevent immediate output of an abnormality signal in the case of the occurrence of slight fault in a microprocessor. CONSTITUTION:A first timer counter 1 which counts a fundamental clock to periodically output a time-over signal, a second timer counter 2 which counts the time-over signal to output a watchdog time-over signal at the time of counting a set number or more, and a gate circuit 3 which inhibits input of the time-over signal to the second timer counter are provided; and when the frequency of the watchdog time-over signal exceeds a set trouble detection frequency, the watchdog time-over signal is held as a status in a fault status register. &Z4: trouble detecting counter, 5: trouble frequency register, 6: comparing circuit, 7: trouble status register, f: to external device.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor failure detection circuit that uses a watchdog timer circuit to detect failures in a microprocessor.

0002

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional microprocessor failure detection circuit disclosed in, for example, Japanese Patent Publication No. 2-18503. Microprocessor bus connecting CPU 18 and other devices, 19
20 is a read-only memory (hereinafter referred to as ROM) that stores a program for operating the CPU 18 via the microprocessor bus 17, and 20 is a random access memory (hereinafter referred to as ROM) that stores data temporarily while the CPU 18 is operating.
10 is an address bus interface circuit connected to the address bus of the microprocessor bus 17, 11 is a first address decode circuit that decodes the address from the address bus interface circuit 10 into a predetermined value, and 12 is a first address. Similarly to the decoding circuit 11,
a second address decoding circuit 13 that decodes the address from the address bus interface circuit 10 into a predetermined value;
is a watchdog timer (hereinafter referred to as WDT) circuit designated by the output of the first address decoding circuit 11;
14 is a gate circuit for notifying the outside of the abnormality detection signal output from the WDT circuit 13; 15 is a data bus interface circuit connected to the data bus of the microprocessor bus 17; and 16 is a second address decode circuit 12.
is a control register specified by the output of here,
The control register 16 is connected to the data bus interface circuit 15.
The gate circuit 14 controls whether or not to notify the outside of the abnormality detection signal from the WDT circuit 13 based on the data content from the WDT circuit 13 . Further, the WDT circuit 13 is connected to the first access and the second access.
An abnormality detection signal is output when this interval time is less than or equal to the lower limit or greater than the upper limit of a predetermined reference time.

Next, the operation will be explained. Immediately after the CPU 18 is reset, the control register 16 is reset and no abnormal signal is output, and after the initial operation of the CPU 18 is completed, the gate circuit 14 is opened by the control register 16 so that the abnormal signal can be output. The power has now been turned on, the system has started up, and the CPU 18 is processing normally.
Assume that initial processing is being performed for a very long time at the time of software reset. Then, the first WD
Since the access time to the T circuit 13 exceeds the reference time,
The monomulti of the WDT circuit 13 emits an abnormal signal due to power supply noise. However, the data previously stored in the ROM 19 is held in the control register 16 by the output of the decode circuit 12 via the data bus interface circuit 15, and therefore the gate circuit 14 remains closed. , the abnormal signal US is not output.

0004

[Problem to be Solved by the Invention] Since the conventional microprocessor failure detection circuit is configured as described above,
There is a problem that an abnormal signal may be output at the same time as the gate circuit 14 is opened by the control register 16 after the initial operation of the CPU 18 is completed, and an abnormal signal is always output even in the case of a minor failure. .

[0005] This invention was made in order to solve the above-mentioned problems, and it prevents an abnormal signal from being output immediately even if the gate circuit is opened, and also performs processing according to the number of CPU failures. The purpose is to obtain a microprocessor fault detection circuit that can be implemented.

[0006]

[Means for Solving the Problems] A microprocessor failure detection circuit according to the present invention includes a first timer counter that counts a basic clock and periodically outputs a time over signal; A second timer counter that outputs a watchdog time-over signal when counting a set number of times or more, and a gate circuit that prohibits the time-over signal from being input to the second timer counter are provided, and the watchdog timer is When the over signal exceeds the set number of failure detections, the watchdog time over signal is held as a status in the failure status register.

[0007]

[Operation] The microprocessor failure detection device according to the present invention inputs the output of the first timer counter constituting the watchdog timer circuit to the second timer counter via the gate circuit, thereby detecting the watchdog time over signal. It functions to avoid unnecessary output and enable the opening and closing of the gate circuit, and to notify that the watchdog time-over signal has been output a predetermined number of times set in the failure count register.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a first timer counter that constitutes a watchdog timer circuit, 2 is a second timer counter that also constitutes a watchdog timer circuit, and 3 is a first timer counter 1 and a second timer counter 2. 4 is an output of the second timer counter 2, and is connected between the gate circuit and the gate circuit for controlling whether or not to input the time-over signal, which is the output of the first timer counter 1, to the second timer counter 2; A fault detection counter that counts watchdog time-over signals, 5 a plurality of fault count registers that set the number of fault detections, and 6 a plurality of comparisons that compare the output of the fault detection counter 4 with the output of the fault count register. The circuit 7 is a failure status register that holds the watchdog time-over signal that is the output of the second timer counter 2 and the output of each comparison circuit 6 as the status. Identical blocks are given the same reference numerals, and redundant explanation thereof will be omitted. Here, the failure detection counter 4 also counts up based on instructions from the CPU 18. In addition, the output of the fault status register 7 is output to CP as interrupt and status.
Not only the U18 but also the external device is notified. Furthermore, (a) is the basic clock input to the first timer counter 1, (b) is the time over signal that is the output of the first timer counter 1, and (c) is the basic clock input from the gate circuit 3 to the second timer counter 1. 2, (d) is a watchdog time-over signal output from the second timer counter 2, and (e) is a failure count-over signal output from the comparison circuit. Further, FIG. 2 is a timing chart showing signals of each part of such a circuit.

Next, the operation will be explained. First, the CPU
18 sets watchdog time-over values to the first timer counter 1 and the second timer counter 2. Here, for example, set the value of watchdog timeover to "6".
Assume that the first timer counter 1 is set to "3" and the second timer counter 2 is set to "2". In addition, the gate circuit 3 allows the time-over signal (b), and the set value of the failure count register 5 is set to "2," and each failure count register 5 and comparison circuit 6 can be configured in plural numbers. However, we will talk about one item here. In actual operation,
First, the first timer counter 1 starts counting the basic clock (a) from point t1 in FIG. Next, t2
When the point is reached, the first timer counter 1 has a count value of "
3'', the time-over signal (b) is output. At this time, since the time-over signal (b) is in the permitted state, the gate circuit 3 outputs the time-over signal (c). Next, at point t3, time-over signals (b), (
c) is output in the same way as at point t2. moreover,
The second timer counter 2 receives the time over signal (c) by 2
Since the time is counted, the watchdog time-over signal (d) is output. At this time, the watchdog time-over signal (d) is notified as a status to the fault status register 7, and also to the CPU 18 and external devices. Next, at point t4, the same operation as at point t2 occurs. Further, when the gate circuit 3 disables the time-over signal (b) at point t5,
Even if the time over signal (b) is output from the first timer counter 1 at point t6, the time over signal (c) is not output because it is prohibited by the gate circuit 3. Next, when the gate circuit 3 enables the time-over signal (b) at the point t7, the time-over signal (b), which is the output from the first timer counter 1, is passed through the gate circuit 3 at the point t8. , is input to the second timer counter 2 as a time-over signal (c). At this time, since the second timer counter 2 counts the time over signal (c) twice, the watchdog time over signal (d) is output. Further, the fault detection counter 4 outputs the count number of watchdog time-over signal (d) "2" to the comparison circuit 6. At this time, since the failure count "2" is set in the failure count register 5, the comparison circuit 6 outputs the failure count over signal (e). The fault count over signal (e) is notified as a status to the fault status register 7, and also to the CPU 18 and external devices. Note that the ROM 19 and RAM 20 are used to store programs and data that operate the CPU 18, and the microprocessor bus 17 is used to store programs and data that operate the CPU 18.
It is used to access other devices such as the first timer counter 1 from U18.

[0010] In the above embodiment, the failure detection counter 4
Although the input to the watchdog time-over signal (d) has been described, the failure detection counter 4 may be incremented by an instruction from the CPU 18, and the same effect as in the above embodiment can be achieved.

[0011]

As described above, according to the present invention, there is provided a first timer counter that counts the basic clock and periodically outputs a time-over signal, and a first timer counter that counts the time-over signal and counts the number of times exceeding a set number of times. A second timer counter that outputs a watchdog time-over signal when the watchdog time-over signal is set, and a gate circuit that prohibits the time-over signal from being input to the second timer counter are provided. When the number of times of detection is exceeded, the watchdog time-over signal is stored as a status in the fault status register, so it is possible to implement fault processing in the microprocessor according to the number of times the fault has occurred. This has the effect of preventing unnecessary output and preventing immediate output of abnormal signals in the event of a minor failure.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a microprocessor failure detection circuit according to one embodiment of the present invention.

FIG. 2 is a timing chart showing signals of each part of the block in FIG. 1;

FIG. 3 is a block diagram illustrating a conventional microprocessor failure detection circuit.

[Explanation of symbols]

1 First timer counter 2 Second timer counter 3 Gate circuit 4 Fault detection counter 5 Fault count register 6 Comparison circuit 7 Fault status register 17 Microprocessor bus 18 Microprocessor (CPU) In the figures, the same reference numerals indicate the same or A considerable portion is shown.

Claims (1)

[Claims] 1. A microprocessor failure detection circuit that detects a failure in a microprocessor by a watchdog timer circuit connected to the microprocessor via a microprocessor bus, the watchdog timer circuit comprising: a basic clock; The watchdog timer circuit includes a first timer counter that counts and periodically outputs a time-over signal, counts the time-over signal, and outputs a watchdog time-over signal when the count exceeds a set number of times. a second timer counter; a gate circuit that prohibits or permits the time-over signal from the first timer-counter circuit to be input to the second timer-counter circuit; and an obstacle for counting the watchdog time-over signal. a detection counter, a failure count register that sets a predetermined failure detection count, a comparison circuit that compares the output of the failure count register with the output of the failure detection counter, and the watchdog time-over signal and the output of the comparison circuit. A microprocessor failure detection circuit comprising: a failure status register that holds as a status.