JPS62272335A - Trouble monitor circuit - Google Patents

Abstract

PURPOSE:To improve the trouble monitor capability by raising alarm when an interval of occurrence between an address value for monitor and a data value for monitor is longer than a certain time. CONSTITUTION:At the time of normalcy, the address value for monitor is inputted to an address bus 6, and the output of a decoder 2 is an active value, and the data value for monitor is inputted to a data bus 7 simultaneously, and the output of a decoder 3 is an active value, and the time of a timer circuit 4 does not expire because the timer is reset when two inputs are simultaneously active, and an alarm signal output 8 is not outputted. In case of runaway of a microprocessor itself or trouble of the address bus, the address value for monitor is not inputted to the address bus 6 and the output of the decoder 2 is not active. In case of trouble of the data bus, the output of the decoder 3 is not active. The timer is not reset in any case because two inputs are not simultaneously active, and the time of the timer circuit 4 expires to output the alarm signal output 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a peripheral circuit that operates a microprocessor, and more particularly to a fault monitoring circuit that detects an abnormality in the operation of a microprocessor.

[Conventional technology]

Conventionally, this type of fault monitoring circuit has consisted of a program that accesses an arbitrary address at a fixed period, and a timer circuit that outputs an alarm if the arbitrary address is not accessed for a fixed period of time or more.

[Problem that the invention seeks to solve]

The conventional fault monitoring circuit described above operates a timer circuit only by accessing an arbitrary address to determine a fault, so it is possible to monitor for runaway microprocessors.
A drawback is that failures in the data bus cannot be detected.

[Means for solving problems]

The fault monitoring circuit of the present invention includes a program that periodically generates an arbitrary address value and an arbitrary data value for monitoring at a constant cycle, a first decode that decodes the address value for monitoring, and a program that decodes the monitoring data. A second decoder decodes the value, the output of the first decoder, and the output of the second decoder are input, and an alarm is issued when the interval between occurrences of the monitoring address value and the monitoring data value exceeds a certain time. It has a timer circuit that generates.

〔Example〕

The present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. 1st
In the figure, 1 is a fault monitoring circuit. 2 is address bus 6
3 is a decoder that inputs the data bus 7 and decodes the monitoring data value, 4 inputs the output of decoder 2 and the output of decoder 3, This is a timer circuit that outputs an alarm signal.

When the microprocessor 5 and its peripheral circuits are operating normally, a means installed in the microprocessor peripheral circuitry periodically accesses any address for monitoring, and at the same time accesses any address for monitoring. By outputting
The monitoring address value is input to the address bus 6, the output of the decoder 2 becomes an active value, and at the same time the data bus 7
The monitoring data value is input to , and the output of decoder 3 becomes the active value, and in timer circuit 4, the timer is reset when two inputs become active at the same time, so there is no timeout and alarm 8 is activated. The signal output is
You can prevent it from being issued.

However, when the microprocessor itself goes out of control or when an address bus failure occurs, the address bus 6 does not become the monitoring address value, and the output of the decoder 2 does not become active. Furthermore, in the event of a data bus failure, the output of the decoder 3 will not become active. In either case, since the two inputs are not active at the same time, the timer is not reset and the timer circuit 4 times out and the alarm signal output 8 is issued.

〔Effect of the invention〕

As explained above, the present invention generates an alarm when the interval between occurrences of a monitoring address value and a monitoring data value exceeds a certain period of time. Buses and data buses can also be monitored, and the fault monitoring capability is improved over conventional fault monitoring circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Fault monitoring circuit, 2... Decoder, 3... Decoder, 4... Timer circuit, 5... Microprocessor, 6... Address bus, 7... Data bus,
8...Alarm signal $1 Figure

Claims (1)

[Claims] Means for periodically generating an arbitrary address value and an arbitrary data value for monitoring at a constant cycle, a first decoder that decodes the address value for monitoring, and a second decoder that decodes the data value for monitoring. and a timer circuit that inputs the output of the first decoder and the output of the second decoder and generates an alarm when the interval between occurrences of the monitoring address value and the monitoring data value exceeds a certain time. fault monitoring circuit.