JPS6361337A - Automatic resetting method - Google Patents

Abstract

PURPOSE:To clear a reading register only with one reading instruction by the circuit of a simple hardware by combining an FF circuit and an OR circuit. CONSTITUTION:When a trouble occurs at respective types of a transmitting device, an alarm signal generated from an alarm generating device is added to the alarm signal input terminal of the first FF9 and the output of the FF9 comes to be '0'. This is read through a gate 2 to a CPU 15 by a reading pulse sent to the gate 2 from an address decoder 14 having a function to output a reading pulse. The reading pulse is also added to the second FF11, activated by the first clock simultaneously added and the signal of '0' is sent from the output of the second FF11 to one side input of an OR circuit 10. The second clock is added to other side input of the OR circuit 10 and the clear pulse as the output of the OR circuit 10 is added to the input terminal of the first FF9.

Description

[Detailed Description of the Invention] [Summary] In an alarm signal readout register using a first flip-flop (hereinafter referred to as FF) and a gate, which is used in communication application equipment using a microcomputer, a second OFF and By providing an OR circuit, when the -degree alarm signal is read, the contents of the read register are automatically cleared, thereby reducing the burden on the software.

[Industrial application field]

The present invention is designed to output an alarm signal when a failure occurs in various transmission devices in communication application equipment using a microcomputer, and the contents of a read register for reading out the alarm signal are automatically read out. This relates to improvements to the automatic reset method for clearing.

In general, in communication system application equipment that uses a microcomputer, a processor (hereinafter referred to as CPU) within the microcomputer reads data and performs work using software instructions sequentially at timings specified by clock pulses. There is.

In this case, when a failure occurs in various transmission devices,
An alarm signal issued from an alarm signal generator (not shown) is input to a read register consisting of an FF and a gate and held there, read into the CPU by a read command from the CPU, and informs the outside of the location of the fault. I'm trying to fix it and restore it.

After reading the alarm signal into the CPU, the contents of the read register mentioned above are cleared so that the alarm signal is not retained, but the circuit for this can be made with simple hardware. It is desirable that the burden of creating software be reduced as much as possible.

[Conventional technology]

FIG. 3 is a block diagram showing the configuration of a conventional read register f17 circuit.

FIG. 4 is a diagram illustrating a conventional automatic reset method using a time chart.

In Fig. 3, the output of FFI is connected to the input terminal d of gate 2.
The output of the gate 2 is connected to the input terminal j of the CPU 5. Then, in the CPU 5, an output terminal Add that outputs a signal indicating an address number representing the device number of the address decoder to be used, and an output terminal E-CLK that outputs a clock are connected to input terminals f and g of the address decoder 3. Input terminal of address decoder 4
Connect to each.

Connect the output of address decoder 3 to input terminal e of gate 2, and connect the output of address decoder 4 to NAND in FF1.
Connect to input terminal C of gate 7.

The circuit consisting of the FFI and gate 2 is called a read register 8.

In normal cases where there is no failure in various transmission devices (not shown), the above-mentioned read register clear circuit 0
The input signal at input terminal a of the FFI remains at "1".

Here, when one of the two inputs of the NAND gates 6 and 7 is "O", the output of the NAND gate becomes "1", and both of the two inputs are "1". When , the output of the NAND gate becomes "0".

Of the two NAND gates 6 and 7 that make up the FFI, the output of NAND gate 7 is in a cleared state.
1'', so due to the nature of NAND gate 6, N
The output of the AND gate 6 becomes "O", and this 0" signal is input to the input terminal of the NAND gate 7, so the N
The output of the AND gate 7, ie, the output of the FFI, is "L".

Now, when a failure occurs in various transmission devices, an alarm signal "O" notifying the failure is input from the alarm signal generating device to the input terminal a of the FFI.

Due to the nature of the NAND gate 6, the output of the gate 6 becomes "1", and '1' is also input to the input terminal of the NAND gate 7. On the other hand, the input terminal C of the NAND gate 7 is
Since “1” is input except when inputting the clear pulse, the output of the NAND gate 7 is “1”.
0”.

The CPU 5 periodically monitors the output of the FFI in order to check the occurrence of failures in various transmission devices.

That is, a signal indicating the address number of the address decoder (for example, FF50) is sent from the output terminal Add of the CPU5.
It is sent to the address decoder 3 which has a function of outputting a read pulse (“0”).

The address decoder 3 determines whether the signal (FF50) from the output terminal Add of the CPU 5 matches the device number (FF50) of the address decoder 3, and determines it using the clock (E-CLK) as shown in FIG. At the right time,
A read pulse (“0” signal) is sent from the same address decoder 3 to the input terminal e of the gate 2, and the gate 2
In this case, the pulse (0') causes the gate 2, which is in a state of blocking passage when the read pulse is not manually applied, to a passing state, and the output of the FFI is inputted to the CPU 5.

The CPU 5 reads the output of the FFI, and when it is determined that an alarm signal "0" is input to the FFI and a failure has occurred in various transmission devices, it instructs the address number from the Add output terminal in order to clear the output status of the FFI. A signal (for example, FF 51) and a clock are sent from the E-CLK output terminal to the address decoder 4, which has a function of outputting a clear pulse (“0”).

In the address decoder 4, the input address number (FF
51) matches the device number (FF51) of the address decoder 4, it outputs a clear pulse (0") at a timing determined by the clock after a certain period of time after the read pulse, as shown in the time chart in FIG. This output is applied to the input terminal C of the N/IND gate 7 in the FFI.

Since the alarm signal "0" is input to the input terminal a of the NAND gate 6, "1" is input to the input terminal of the NAND gate 7. When "0" is input to the input terminal C of the NAND gate 7, the output of the same NANO gate 7 becomes "1", and the output of the FFI changes from the state where the alarm signal ("0") is held to the state M ( “1”).

At this time, as shown by the dotted line in a circle in Figure 4, if the alarm signal is instantaneous (for example, the repetition frequency of the readout pulse is approximately 10 milliseconds and the width of the alarm signal is several nanoseconds), ), the output of the FFI is cleared by the clear pulse.

On the other hand, as shown surrounded by a dashed line in Figure 4, if the alarm signal period continues for a long time, the clear pulse instantly clears the alarm signal for a period determined by the pulse width of the clear pulse, and the clear pulse ("O") When the FFI is no longer cleared, the output of the FFI returns to its original uncleared state (“0”). After the alarm signal disappears, the output of the FFI is cleared by a clear pulse determined by the next timing pulse.

In this way, the read register is cleared.

[Problem that the invention seeks to solve]

However, in the conventional automatic reset method described above, software created in the CPU reads the input alarm signal and issues the next command at a timing determined by the clock to clear the read register.

However, this had the problem that the burden of software production was large.

[Means for solving problems]

The above problem is that the -OFF output is connected to the CP via the gate.
In the read register configured to send signals to U, a second OFF having input terminals for signals and clocks, and an output terminal for signals, and an OR circuit having two input terminals are provided, and the signal of the second OFF is provided. The above readout signal is applied to the FF input terminal, and the signal applied to the FF is activated by the first clock applied to the second OFF clock input terminal, and the output signal is sent to the OR circuit. In addition to one input terminal, a second clock is applied to the other input terminal of the OR circuit, and the output of the OR circuit is applied to the input terminal to which the clear pulse of the first FF is applied. Solved by automatic reset method.

[Effect]

According to the present invention, when a failure occurs in various transmission devices,
An alarm signal ("0") output from the alarm generator is applied to the -OFF alarm signal input terminal, and the output of the FFI becomes "0". This is the read pulse (“0”
) is sent to the gate from the address decoder, which has the function of outputting CP.
Load into U.

The above read pulse is also applied to the second OFF, and activated by the first clock applied at the same time, an "O" signal is sent from the output of the second OFF to one input of the OR circuit.

On the other hand, a second clock is applied to the other input of the OR circuit, and a clear pulse ("0'"
) is applied to the input terminal to which the -th OFF clear pulse is applied.

As a result, the output of the FFI becomes "1", the state where the alarm signal ("0") is held is released, and the state is automatically cleared (1).

〔Example〕

FIG. 1 is a block diagram showing the configuration of a read register clear circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating the automatic reset method according to the embodiment of the present invention using a time chart.

The same reference numerals refer to the same objects throughout the design.

In FIG. 1, it is assumed that an alarm signal "0" issued from the alarm generating device is input to the input terminal a of the first flip-flop 9 due to a failure in the transmission device.

As in the case of the conventional example, the output signal of the first FF 9 is set to "L" when cleared by a clear pulse.

In the CPU15, a signal indicating an address number (for example, FF52) is sent from the output terminal Add toward the address decoder 14 together with a clock (E-CLK).

When the address decoder 14, which has the function of outputting a read pulse when activated by the clock (E-CLK), determines that the signal indicating the input address number and the device number (FF52) of the address decoder 14 are -G. , and sends out a read signal (“0゛) to the input terminal e of the gate 2 and the input terminal of the second OFF 11.

Gate 2 receives a read pulse (“
O”) to make the same gate 2 pass through, and the -OF
The output signal of F9 is input to the CPU 15 through the same gate 2.

A read signal (“O”) is also applied to the input terminal of the second OFF11.
) is input, and as shown in Figure 2, the input level is held by E-CLK which is inverted and -CLK (arrow ↑ shown in the figure), and "0" is output from the second OFF output terminal Q.
” is output, and the same signal is input to the input terminal m of the OR circuit 10.

On the other hand, the input terminal k of the OR circuit 10 has E-CLK.
The Q-clock (hereinafter referred to as Q-CLK) shifted by 174 cycles is inverted by the inverter 13, and the Q-ct and K
is input.

As shown by diagonal lines in FIG. 2, a clear pulse of "O" is output to the input of the OR circuit 10 only during the period when and m are simultaneously "0". This '0' signal is input to the -OFF9 input terminal C.

In this way, when the -degree alarm signal is read out, a readout register clear pulse is automatically output at approximately 1/4 cycles yj2& of the readout pulse.

〔Effect of the invention〕

As explained above, according to the present invention, unlike the conventional example, the CP
A simple hardware circuit can clear the read register with just one read command, without using two command signals from U.

As a result, the burden of software production can be reduced and the software can be made into a single piece.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of the read register clear circuit according to the embodiment of the present invention, Fig. 2 is a diagram explaining the automatic reset method of the embodiment of the present invention using a time chart, and Fig. 3 is the readout of the conventional example. FIG. 4 is a block diagram showing the configuration of a register clear circuit. FIG. 4 is a diagram illustrating a conventional automatic reset method using a time chart. In the figure, the engineering is FF. 2 is a gate, 3.4.14 is an address decoder, and 5.15 is a CPU. 6.7 is a NAND gate, 8 is a read register, and 9 is -OFF. 10 is an OR circuit, 11 is a second OFF. 12.13 indicates an inverter.

Claims (1)

[Claims] Having two input terminals, applying a signal to one input terminal,
The output of the first flip-flop (9), which applies a clear pulse to the other input terminal, is applied to one input terminal of a gate (2) having two input terminals; In a circuit in which the output of the first flip-flop (9) is passed through the gate only when a read signal is applied to the input terminal, input terminals for signals and clocks, and output terminals for signals are connected. A second flip-flop (11) having a second flip-flop (11) and an OR circuit (10) having two input terminals are provided, and the readout signal is applied to the signal input terminal of the second flip-flop (11), and It is activated by the first clock applied to the clock input terminal of the flip-flop (11), outputs the signal applied to the flip-flop (11), and sends the output signal to one input terminal of the OR circuit (10). In addition, a second clock is applied to the other input terminal of the OR circuit (10), and the output of the OR circuit (10) is applied to the input terminal to which the clear pulse of the first flip-flop (9) is applied. An automatic reset method characterized by: