JPH04148246A - Watchdog timer - Google Patents

Abstract

PURPOSE:To enable a processor to save or external-output necessary data under the situation of the occurrence of a fault through interruption by generating the interruption for the processor at the time of watchdog timer overflow, and generating reset definite time later. CONSTITUTION:The timer consists of an oscillator 1, an interruption timer 2, and a reset timer 3. In the case that a processor part 7 can respond to the interruption, it executes the memory save of the data necessary for the fault analysis of a register in the processor or a task in running or the save of a disk or the output of an alarm or the output of fault data to the outside by the interruption, and stops operation. Then, it waits for the generation of the reset. After that, the processor part 7 is initialized by the generation of the reset, and executes re-start processing, but a time interval from the generation of the interruption to the generation of the reset is set to be time during which this processing can be executed. Thus, the processor can execute the save or the external output of the necessary data under the situation of the occurrence of the fault.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique for monitoring the normal operation of a processor and restarting the processor when a failure occurs, and particularly relates to a watchdog timer.

U Prior Art Conventionally, this type of watchdog timer has been of a type that outputs a reset signal to the processor when the timer overflows.

[Problem to be solved by the invention M] However, in such a conventional device, the processor is reset when the timer overflows, so if the periodic timer cannot be cleared due to a bug in the program, it is possible to solve the problem in which program. It was difficult to analyze whether this occurred. Furthermore, in the case of hardware stacks, etc., there is a problem in that a reset is applied, making it difficult to analyze the stack state.

[Means for Solving the Problems] In order to solve such problems, the present invention provides a means for generating an interrupt to a processor when a timer overflow occurs, and a means for generating a reset to the processor after a certain period of time. have the means.

[Operation] When the timer overflows, the processor is interrupted and then reset.

[Implementation N] The figure is a block diagram showing one embodiment of the present invention.

The oscillator 1 generates a basic clock for the watchdog timer circuit, and the interrupt timer 2, which counts up the interrupt timer 2 and reset timer 3, receives a signal from the processor section 7 via the watchdog timer clear command signal line 4. During normal operation, the timer clear command is entered periodically to prevent the interrupt timer from overflowing.

If the processor malfunctions and no clear command is received, the interrupt timer overflows and
An interrupt is generated in the processor section 7 via the interrupt signal line 5. This enables the reset timer 3.

The enabled reset timer 3 overflows after a certain period of time and causes the processor section 7 to generate a reset via the reset signal line 6. processor a
17 operates as follows in response to the occurrence of the interrupt and reset.

If the processor unit 7 is capable of responding to the interrupt, the interrupt causes registers in the processor, data necessary for failure analysis of the task being sent to be saved in memory or disk, alarm output to the outside, or failure to occur. Outputs data, stops operation, and waits for reset to occur.

Thereafter, the processor section 7 is initialized by the occurrence of a reset, and the time interval from the occurrence of the 0 interrupt for re-#R processing to the occurrence of the reset is set to a time during which the processing can be performed. If a serious failure occurs in the processor section and the above-mentioned processing is impossible due to an interrupt, the processor section is initialized by the generation of a reset after a fixed period of time and resumes processing.

[Effects of the Invention] As explained above, the present invention generates an interrupt for the processor when the watchdog timer overflows, and generates a reset after a certain period of time. This has the effect of making it possible to save or externally output necessary data below.

[Brief explanation of drawings]

The figure is a block diagram showing one embodiment of the present invention. 1.--Oscillator, 2--.Talk timer, 3.--
-Reset timer, 7-...processor section. Patent applicant: NEC Corporation

Claims (1)

[Scope of Claims] A watchdog timer for monitoring the normal operation of a processor includes interrupt means for generating an interrupt to the processor when the processor does not periodically clear the timer and the timer for a specified time overflows; A watchdog timer characterized in that it generates a signal for resetting a processor after a certain period of time after the interrupt, and is equipped with a reset means.