JPH0452977B2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to the improvement of an abnormality detection circuit for the operating state of a CPU, and in particular to the abnormality detection of a system that uses a CMOS type CPU and whose state is controlled by software. and recovery from an abnormal state.

(Prior art) Conventionally, in order to detect and recover from an abnormal state in a circuit including a CPU, a method such as the one shown in Figure 2 has been used.
CPU supervisor/reset circuits were known. In FIG. 2, 8 is a CPU, 9 is a counter, 13 is an inverter, and 14 is an AND gate.

In the example shown in FIG. 2, the CPU 8 outputs a reset signal (ANRST signal) to the external counter 9 at least once in a certain period of time, and when the CPU 8 no longer outputs the reset signal, the external counter 9 outputs a reset signal (ANRST signal). The configuration is such that the counter is raised and the CPU 8 is reset. That is, the output of counter 9 is applied to AND gate 14 through inverter 13. When the output of the counter 9 becomes low level, the output of the inverter 13 becomes high level, and the AND gate 14 calculates the logical product. Logic functions become signals to CPU8
added to.

In the example shown in FIG. 2, when the CPU 8 no longer outputs a reset signal to the external counter 9,
It is assumed that CPU 8 has entered an abnormal state.

(Problems to be Solved by the Invention) In the CPU supervisor/reset circuit according to the prior art described above, the CPU outputs a reset signal to an external counter every certain period, so the CPU does not operate during this period. state. If you try to shorten the abnormal condition detection cycle, the CPU
Since it is also necessary to shorten the period of the reset signal output from the CPU, the time rate in which the CPU is in standby mode also decreases, which increases current consumption.

It is also necessary to carefully consider which program task is best for outputting a CPU reset signal when the CPU is in operation. For example, if the interrupt task is configured to output a reset signal, the main task is out of control, but the interrupt task is operating normally. The interrupt task does not detect this state as an abnormal state.

In this way, traditional CPU supervisor/
Detecting abnormal conditions using a reset circuit has the disadvantage that, firstly, shortening the detection cycle will also reduce the CPU's standby time rate.Secondly, it is necessary to carefully consider which program task will perform CPU reset signal output processing. There is a drawback that it is necessary to do so.

The purpose of the present invention is to constantly monitor the CPU standby time rate and, when the CPU standby time rate exceeds a predetermined certain range, to eliminate the above-mentioned drawbacks by resetting or interrupting the CPU. It is an object of the present invention to provide a CPU supervisor/reset circuit which has a high CPU standby time rate and which is configured to uniquely determine the task of a reset signal output process.

(Means for Solving the Problems) A CPU supervisor/reset circuit according to the present invention is capable of outputting a control signal indicating whether the CPU is in an operating state or a standby state, and includes: It is constructed by comprising a counting means, a comparing means, and a reset means.

The counting means includes a sampling circuit, a counter, a timing generation circuit, and a latch circuit. In the sampling circuit, the control signal in the active state is sampled by the clock signal output from the timing circuit and sent to the counter, and the counter The output of the sampling circuit is counted for a certain period of time regulated by the timing circuit, and the latch circuit holds the output of the counter for a certain period of time regulated by the timing circuit.
The control signal is configured to constantly monitor the time rate at which the control signal is active by outputting it to a comparison circuit.

The comparison means is configured to compare the output of the counting means with a reference value and send an alarm signal to the CPU when the time rate during which the control signal is active exceeds a certain range.

The reset means is configured to interrupt or reset the CPU when the alarm signal becomes active.

(Example) Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a CPU supervisor/reset circuit according to the present invention. In Figure 1, 11 and 12 are respectively
AND gate, 2 is a counter, 3 is a timing generation circuit, 4 is a latch circuit, 5 is a comparison circuit, 6 is a supervisor/reset circuit according to the present invention, 7 is a
It is the CPU.

In FIG. 1, the supervisor/reset circuit 6 constantly monitors the time rate of the signal from the CPU 7, and when the time rate of the signal exceeds a predetermined range, it considers this to be an abnormal state and sends the signal to the CPU 7. Outputs a signal to the

CLK signal generated by timing generation circuit 3,
The signal output from the CPU 7 is input to the AND gate 11. The AND gate 11 performs sampling, calculates the logical product of the above two signals, and outputs the result to the counter 2. The CONT1 signal and CONT2 signal generated by the timing generation circuit 3 are respectively applied to the counter 2 and the latch circuit 4 over a certain period of time.
is input. The latch circuit 4 latches the signal during the period in which the CONT2 signal is being sent.

Therefore, the comparator circuit 5 checks whether the value set in the counter 2 does not exceed a predetermined range, and outputs a signal if the value exceeds the predetermined range. clear. The reset terminal of CPU7 has a signal and a power-on reset signal (
It is configured by an AND gate 12 so that a logical product with a signal) is input. Therefore, when the signal becomes active, the CPU 7 is reset.

(Effects of the Invention) As explained above, the present invention constantly monitors the CPU standby time rate, and when the CPU standby time rate exceeds a certain range, resets or interrupts the CPU. Since there is no need to put the device into an operating state every certain period and output a signal to an external circuit, there is an effect that current consumption can be reduced accordingly.

Furthermore, if the CPU wait time rate is within a certain range, the main task and interrupt task are operating in the correct relationship due to the CPU software. Therefore, monitoring the CPU standby time rate has the effect that it is possible to monitor to some extent whether the CPU software is operating correctly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a CPU supervisor/reset circuit according to the present invention. FIG. 2 is a block diagram showing an example of a CPU supervisor/reset circuit according to the prior art. 11, 12, 14...AND gate, 2, 9...
...Counter, 3...Timing generation circuit, 4...
Latch circuit, 5... Comparison circuit, 6... Supervisor/reset circuit, 7, 8... CPU, 13...
...Inverter.

Claims (1)

[Scope of Claims] 1. A CPU supervisor/reset circuit capable of outputting a control signal indicating whether the CPU is in an operating state or a standby state, the time rate during which the control signal is active. a counting means for constantly monitoring the output of the counting means; a comparison means for outputting an alarm signal when the time rate during which the control signal is active exceeds a certain range by comparing the output of the counting means with a reference value; When the signal becomes active,
a reset means for outputting a signal to the CPU to interrupt or reset the CPU; the counting means includes a sampling circuit, a counter, a timing generation circuit, and a latch circuit; The active control signal is sampled by a clock signal output from the circuit and sent to a counter, and the counter counts the output of the sampling circuit for a certain period of time regulated by the timing generation circuit. A supervisor/reset circuit for a CPU, characterized in that the latch circuit is configured to hold the output of the counter for a certain period of time regulated by the timing generation circuit and output it to the comparison circuit.