RU1797122C - Device for restart and testing power supply of microcomputer - Google Patents

Abstract

The invention can be used in microprocessor systems for monitoring the system channel of a computer in real time during power ups and downs. The purpose of the invention is to increase the reliability of the device. Using the input signals, the operation of the system channel of the microcomputer is monitored. These signals are processed using three OR-NOT elements, the first NOT element and a trigger that triggers the one-shot. The presence of a high level at the output of a single vibrator indicates the correct operation of the microcomputer, which is indicated by the second element NOT by an indicator. In program mode, when a system channel fails, the specified trigger is set to one of the stable states. At the output of the single-radiator, a low level appears allowing the restart of the microcomputer. Restarting is performed using two binary counters, a decoder, two OR elements, a delay element, two triggers and formers. Moreover, in case of malfunctions in the system channel, a predetermined number of microcomputer restarts are performed without resetting to the initial state of the nodes and blocks of the microprocessor system. The overvoltage or undervoltage levels of the microcomputer power supply are controlled by a voltage control unit, which includes a reference voltage source, two comparators, an NAND element, an NAND element, an optoelectronic switch, and a delay element. In this case, the necessary sequence of generating emergency stop signals for a microcomputer having an O-bus system channel is carried out during power-ups and power failures and system channel failures. 1 s.p. crystals, 4 ill., 1 tab. Oooh

Description

The invention relates to automation and computer technology and can be used in microprocessor systems to monitor the operation of microcomputers in real time at power ups and downs.

The aim of the invention is to increase the reliability of the device.

On Fig, 1 presents a functional diagram of a device; Figures 2-4 are timing diagrams of the operation of the device upon power-up and power failure, the operation of the write and read synchronization elements of the device, and the control of the microcomputer restart software modes.

The device contains inputs 1-8 of the device, the second element OR-NO 9, the first element NOT (inverter) 10, the third element OR-NOT 11, the first counter 12, the decoder 13, the first element OR-NOT 14, the first resistor 15 of the voltage divider , power supply 16, voltage monitoring unit 17, second voltage divider resistor 18, second delay element 19, AND-NOT element 20, first-third OR elements 21, 22 and 23, first delay element 24, second trigger 25, second counter 26, the first driver 27 stop signal, the output 28 of the accident power source of the device, the first trigger 29, h the fourth element OR 30, the second driver 31 stop signal, the output 32 of the alarm signal power supply of the device, the third trigger 33, one-shot 34, the second element NOT (inverter) 35, indicator 36.

The voltage monitoring unit 1-7 comprises comparators 37 and 38, a reference voltage source 39, an AND-NOT element 40, an optoelectronic switch 41, a NOT element (inverter) 42, a delay element 43.

If it is necessary to coordinate the inputs 1 ... 5 of the device with the signals of the system channel of the microcomputer, buffer elements with an open collector can be used (in Fig. 1 these elements are not indicated). In this case, the outputs of these elements through a resistor of the order of 2 ... 3 kOhm must be connected to a supply voltage of +5 V. This voltage is generated at the second output of the power supply T6, to the input of which, for example, a network voltage equal to + 27 V, The +5 V voltage regulator of source 16 can be implemented as a simple parametric stabilizer with a capacitor of the order of 15. ,,, 100 μF at the output or using the 142ENZ chip, +10 V circuit consumption generated at the first output of the source 16, does not exceed 0.03 A. The stabilizer n Apr. +108 can also be implemented as a simple parametric MLI stabilizer using 142ENZ chip. Depending on the type of element base used and, accordingly, the consumption of the device, other options for constructing the source 16 are possible.

As shapers 27.31, repeaters 564PU4 or a dual inverter made on a 1NT251 transistor matrix can be used. As an inverter 35, a 564LN2 chip or an inverter made also on a 1NT25L chip can be used.

Indicator 36 is a series circuit of an AL307B type LED and a resistor, the first output of a resistor of the order of 500 Ohms

connected to the +5 V power supply, the second output of the resistor is connected to the anode of the LED, the cathode of which is the input of the indicator 36, Comparators 37, 38 can be performed on operating rooms

amplifiers x 154UD1, and equal to 30 kOhm resistors are installed on the inverting and non-inverting inputs of these amplifiers. Source 39 is made in the form of two resistive

5 voltage dividers that form the reference voltages Uimax 5.5 V and L) 2min 4.5 V, An optoelectronic logic signal switch is used as the optoelectronic switch 41

0 249LP1B, 564AG1 microcircuit was used as a single-shot (standby multivibrator) with restart. The duration of the single-shot pulse is chosen equal to (0.1 ... 0.6) Timer, where

5 Taymera - period of repetition of the MPVSN timer signal received at input 4 of the device. And Tytaymera. 50 ... 250 MS. The values of resistors 15, 18 are 10.0 ... 15.0 kOhm. Delay element 24 may

0 be implemented as an integrating chain ..

The time constant of element 24 is 4 ... 6 ms. The time delay of the signal by the element 43 when the power is turned on and appears on

5, its logical unit signal output is 10 ... 12 ms. The delay time of the zero input signal by element 43 (when a zero potential appears at its input) is approximately 51 μs, i.e. the time

The delay 0 of element 43 is different for the passage of logic zero and logic one signals.

The device provides restart control microcomputer having a system

Channel 5, compatible with the information transfer channel of the Microcomputer Electronics 60 bus (Electronics 81 B, KM 1801VM1, KM1801 VM2, KM1801 VMZ, 1806VM2. 1806VMZ), which is a simplified version of the Common Bus interface (TOST 26765.51-86). The inputs 1 ... 5 and the outputs 28, 32 of the device are connected to the system channel according to the table.

Input 6 is supplied with DC voltage. At input 7, a logic zero signal can block (disable) the operation of the microcomputer without disconnecting the mains voltage. This input can also be used to connect additional

health signals of nodes of microprocessor systems. Input 8 receives a +5 V supply voltage of the microcomputer (controlled voltage).

The device operates as follows.

After applying the mains voltage and the appearance of the supply voltage at the output of the power source 16, a signal of a logical unit is generated at the output of the AND-NOT 20 element, which performs the initial installation of the device nodes (Fig. 2). In this case, logic zero signals are generated at the output of triggers 25.29, and logic zero signals are also set at the outputs of counters 12, 26. At the outputs 28.32, emergency stop signals are generated in the form of a logical zero, which corresponds to the active level of the microcomputer bus. As soon as the supply voltage of the microcomputer. at the input 8 it reaches the operating level, at the inputs 1 .- .. 3 the volt signals of the logical unit, and at the input 4 - the signal from the timer. At the same time, at the output of block 17, after a time determined by the time constant of the delay element 43, a signal of a logical unit will appear. In the presence of the same signal from the output of the delay element 19 at the output of the AND-NOT 20 element, the logic zero signal is received and the initial installation of all nodes of the device stops.

Simultaneously with the appearance of the output signal from the output 28, the microcomputer generates dl. system channel low-level signal MUSTN, which is used for initial installation. all devices connected to the channel. This signal is generated each time the power is turned on according to the MAIPN signal. In this case, regardless of the potential at the input 5 of the device, a logic zero signal is set at the reset input of the counter 12. And this counter recalculates the number of pulses of the signal at input 4. When a fourth pulse of the MPVSN signal arrives at input 4, a signal appears at the second output of decoder t3 logical unit, setting the trigger 25 to the state of the logical unit, and the signal MAIPN at the output 28 becomes passive (high). At the same time, indicator 36 turns on. The microcomputer responds with a signal to read the IARS signal by reading the signal MUSTN and waits to receive the signal MASTP at output 32, which becomes passive by the presence of the sixth pulse of the signal at input 4. At the same time, the signal of the logical unit from the output of the decoder 13 trigger 29 set to zero state. After the signal is received, the MASP is executed.

the microprogram for selecting the start mode and the microcomputer proceeds to the execution of the microprogram corresponding to the selected operating mode. Those. when the signal 5 of a logical unit is set at input 5, the microcomputer proceeds to the execution of the work program (program mode). In the presence of a logic zero signal at input 5, the microcomputer enters the communication mode with the console terminal,

When the supply voltage of the microcomputer is overestimated (underestimated) or the signal at input 6 disappears (Fig. 2), the emitting diode of the optoelectronic switch 41 is de-energized and at its output after a time of not more than 0.1 ms, a zero potential appears, which provides setting the active signal level at the outputs 28, 32 of the device. Moreover, when an active level of the MASF signal appears, the microcomputer switches to the microprogram for processing the power failure. The value of the processing time of this firmware does not exceed 4 ms (this time is determined by the delay time of the element. 24), after which the trigger 25 is set to the logical zero state and a low level of the SID signal at output 28 appears. Then again

0 microcomputer performs a reset of all nodes connected to the system channel, and stops its work. Those. over a period of the order of S ... 7 ms, the power source 16 and the power supply of the microcomputer must store operating voltage at their outputs. In this case, there is no indication of the operation of the microcomputer on the indicator 36. If the operating voltage of the microcomputer is restored in the range determined by the 0 voltages at the outputs of the reference voltage source 39, then the signals are formed at the outputs of the comparators 37, 38. logical unit values determined by the supply voltage of these comparators,

5, which leads to the presence of a zero potential at the output of the AND-NOT 40 element. A current flows through the emitting diode of the switch 41 and a logic zero signal appears at the output of this switch. Block output

0 17 there is a logical unit signal. When an overestimated (underestimated) supply voltage of the microcomputer with respect to the output signals of the reference voltage source 39 appears at the output of the comparator 37 (38), a logic zero signal appears; which leads to the appearance of a high level signal at the output of the AND-NOT 40 element. the radiating diode of the optoelectronic switch 41 is de-energized. At the exit . of the switch 41, a signal of a logical unit appears, and at the output of block 17, a signal of a logical zero, which leads to the initial state of the device nodes and shutdown, as mentioned above, of the microcomputer.

If the operating voltage of the microcomputer is present and the MOSTN signal corresponding to a low level is set at input 5, the microcomputer enters communication mode with the remote terminal, and the microcomputer reads the status of the data registers and the status of the remote terminal and keyboard. This access to external devices takes place in a read cycle. Those. in the system channel there is an MDCHT signal, which is fed to input 3 of the device. The recording signal of the MDCH input to the input 1 of the device is absent (a logical unit signal is set in the system channel). The MDZN signal can become active, in this case, only when the system channel is in direct access mode, the duration of which does not exceed 3 ... 4 μs. However, when operating in direct access mode at the active (low) level of the MPZN signal at input 2, the passage of the MDZN and MDCHT signals to the inputs of the trigger 33 is prohibited, which leads to the installation of this trigger in one of the stable states (Fig. 3). The single-vibrator 34 is not started and a logical zero signal is present at the input of the OR element 23. From the output of the OR 23 element, a logical unit signal is received, which prohibits the operation of the counter 12, which blocks the restart of the microcomputer. When the MOSTN signal appears at input 5 with a logic unit level, a logic zero signal appears at the output of the USB-NOT 14 element, which leads to the presence of the same signal at the reset input of the binary counter 12 and the microcomputer restarts. When the work program ( the program mode of operation of the microcomputer) in the system channel, the microcomputer is accessed to various blocks and devices of the microprocessor system as a whole. Those. there is an alternation of the cycles of writing and reading information (entering into registers, reading from registers, etc.). The duration of the time-spaced signals MDSN, MDSTN is approximately 1 ... 1.5 μs. The repetition rate of the MFTC signals is approximately 50 ... 400 kHz. The signal repetition rate of the MDCH signals is usually 3 ... 10 times lower. The repetition rate of these signals is determined by the operating frequency of the microcomputer, the type and volume of the work program, i.e. when executing a work program on trigger inputs 33

sequences of write and read signals are received. The presence of these signals leads to trigger switching

33. start and restart the single vibrator

34. Moreover, the start and restart of the one-shot 34 is carried out both on the positive (from zero to one), and on the negative (from one to zero) voltage drop of the trigger 33. At the output of the one-shot 34 a steady signal of a logical unit appears, blocking the restart microcomputer. The signal from the output of the one-shot 34 through the OR element 30 is fed to the input of the inverter 35, including the indicator 36. A steady glow of the indicator 36 indicates the execution of the work program and the absence of freezes and malfunctions in the operation of the microcomputer.

It should be noted that when the microcomputer operates in program mode, interruption conditions may arise, the processing of which is not provided for by standard mathematical software. Such conditions (fatal or failed states) include a double error when accessing the system channel, an error in transmitting an interrupt vector, an error during memory regeneration, a freezing of the system channel,

In these situations, microcomputers of the type Electronics 60 and Electronics 81 B go into communication mode with the console terminal. Those. begin to read, as indicated above, the status of the data registers and the state of the remote terminal and keyboard. Since such devices are absent in the onboard microprocessor systems, the microcomputer stops executing the work program and continues to work in communication mode with the console terminal, which leads to the absence of the MDCH signal and the recording cycle. In this case, the trigger 33 is set in one of the stable states. At the output of the single-shot 34, a zero potential appears, allowing the counter 12 to work. The presence of a zero potential at the output of the single-shot 34 in program mode indicates the presence of a fatal situation in the system channel, the termination of the work program or the failure of the microcomputer,

If during the time corresponding to t 3 of the Timer the alternation of the MDZN and MDCHTN signals does not resume, then the signal from the first output of the decoder 13 sets the trigger 29 to the zero state and, accordingly, the output signal MASPN at the output 32. In this case, the microcomputer switches to power failure interrupt processing routine. At the same time, the state of the counter 26 is increased by one. Next, the fourth pulse of the timer signal from the second output of the decoder 13 confirms the presence of the level of a logical unit at the output of the trigger 25 and, accordingly, the presence of a passive (high) level of the signal of the IAMS at the output 28. At the same time, during the timer, during the period between the occurrence at the input 4 of the fourth and fifth pulses of the MPVSN signal, the indicator 36 is illuminated by the signal from the second output of the decoder 13, supplied through the IL AND 30 element to the input of the inverter 35.

The sixth pulse of the timer signal from the third output of the decoder 13 by the logical unit signal sets the trigger 29 to the logical unit state, which corresponds to the presence of a high level at the output of the driver 31 and the output 32 of the device. The appearance of a high level signal MASPN indicates the normal state of the mains supply, and the microcomputer again proceeds with the start-up microprogram followed by the work program. In this case, the operation of resetting to the initial state of the units and nodes of the microprocessor system is not performed, which allows, for example, saving current information in RAM and generally improving the noise immunity and reliability of the system as a whole. The presence of a restart without resetting to the initial state of the blocks and units of the microprocessor system is recorded, as indicated above, by the counter 26 by increasing its state, i.e. counter 26 counts the amount of restart data.

The number of restarts is chosen experimentally, depending on the features of the microprocessor system and equal to n, where K is an integer. Figure 4 shows the timing diagram of the operation of the nodes of the device for K 1. In this case, when performing a second restart and the active level appears at the output 32 of the device, the output of the counter 26 is a signal of a logical unit, which through element 21 and the delay element . 24 sets the trigger 25 to a state of logical zero, which leads, as indicated above, to the appearance of the active level of the IARS signal at the output 28 of the device, as well as the signal MUSTN at the output of the microcomputer, which reset the microprocessor system nodes to the initial state . Reset occurs during one signal period

MPVSN timer. At the same time, the reset (resetting) of the counter 26 is carried out. Next, the signal from the second output of the decoder 13 sets the trigger 25 and the IARC signal to the logical unit state. The operation of resetting the nodes connected to the system channel of the microcomputer is also stopped by setting the trigger 29 to the logical unit state, which corresponds to the passive (high) state of the MASP signal at the output of the device 32; the microcomputer again proceeds with the start-up microprogram followed by the subsequent execution of the working program5. If the microcomputer does not proceed with the execution of the work program and the restart process is carried out, the indicator 36 will periodically light up during the time ti

0. Timer with a pause t2 7 Timer, which indicates a failure of the microprocessor system. It should be noted that when debugging a work program on a microcomputer in communication mode with a remote terminal,

5 i.e. when it is executed step by step, an indication of the execution of individual program instructions is provided in the device. SUMMARY OF THE INVENTION 1. A device for restarting and monitoring the power supply of a microcomputer containing a power source, the first output connected to the working power input of the voltage control unit, three triggers, two OR elements, the first element NOT, the element NAND, the output connected to the first input of the first OR element, the first OR-NOT element and two stop signal drivers, the first input of the first OR-NOT element connected to the inverse

0 by the output of the first trigger, distinguishing it in that, in order to increase the reliability of the device, two counters, a decoder, an indicator, two OR elements, two delay elements, one vibrator, the second element NOT, two OR elements are introduced into it NOT and a voltage divider, and the output of the first counter is connected to the input of the decoder, the first output of which is connected to the first input of the second

0 OR element connected by the output to the reset input of the first trigger, the inverse output of which is connected to the counting input of the second counter, the reset input and output of which are connected respectively to the inverse 5 output of the second trigger and the second input of the first OR element, the output of which through the first delay element is connected to the reset input of the second trigger, the output of the third trigger through a single vibrator is connected to the first inputs of the third and

of the fourth OR element, the reset and installation inputs of the third trigger are connected respectively to the outputs of the second and third OR-NOT elements, the first inputs of which are connected respectively to the output of the first element NOT, and the second inputs are respectively the inputs for writing and reading device synchronization, the output of the element AND-NOT connected to the second inputs of the second and third OR elements, the third input and output of the third OR element are connected respectively to the output of the first OR-NOT element and the reset input of the first counter, indicator input through the second element is NOT connected to the output of the fourth OR element, the second input of which is connected to the installation input of the second trigger and the second output of the decoder, the third output connected to the installation input of the first trigger, the direct outputs of the first and second triggers are connected respectively through the second and first signal conditioners stop with the outputs of the emergency power supply and the power source of the device, the second input of the first element OR is NOT the input of the stop signal of the device and is connected via a voltage divider connected to the input of the input delay element and the input of the device blocking signal, the midpoint of the voltage divider is connected to the second output of the power source, the mains input of which is connected to the mains input of the device and the mains input of the voltage control unit, the controlled voltage input whose power supply is the input of the controlled voltage of the device, and the output is connected to the first input of the NAND element, the second input of which is connected to the output of the second delay element, the counting input of the first etchika is input interruption signal from the timer device.

2. The device according to claim 1, with the proviso that the voltage monitoring unit comprises two comparators, a reference voltage source, an AND-NOT element, an optoelectronic switch, an NOT element and a delay element moreover, the inverse input of the first and non-inverse inputs of the second comparators are combined and are the input of the monitored power supply of the unit, the input of the reference voltage and the first conclusions of the power voltage of the comparators are combined and are the input of the working lithium of the unit, the second voltage pins of the comparators are connected with a common power supply bus, the non-inverse input of the first comparator is connected to the first output of the reference voltage source, the second output of which is connected to the inverse input of the second comparator, the outputs of the first and second comparators are connected respectively to the first and second inputs of the AND gate NOT connected by the output with the cathode of the emitting diode of the optoelectronic switch, the anode of which is the input of the power supply of the unit, the output of the optoelectronic switch through the element is NOT connected to the input of the delay element, the output to which is the output of the block.

FIG. 2