JPH0215320A - Clock mechanism control system - Google Patents

Abstract

PURPOSE:To prevent program execution from being influenced by abnormality processing time by supplying a reference pulse with a short period at the time of restarting the counting of one counter, and when the count value of the counter reaches the same count value as that of the other counter, supplying an original reference pulse. CONSTITUTION:In a normal state, a clock counter 2 and a backup counter 4 count up clock reference pulses outputted from a reference pulse generator 1 at the time of reference clocking. When a hardware abnormality processing signal is inputted, the counter 2 is stopped by an output from an inversion gate 7. During the period, the counter 4 continues clock operation. When a hardware abnormality processing end signal is inputted, a rapid clock reference pulses generated from a rapid clock reference pulse generator 3 are supplied to the counter 2. When both the count values of the counters 2, 4 reach the same count value, a coincidence signal from a comparator 6 is made significant and the system is restored to a state set up before the generation of hardware abnormality.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention provides a clock (time) in an electronic computer system.
This relates to the control method of the mechanism.

[Conventional technology]

2. Description of the Related Art In computer systems that include a central processing unit, a main memory, input/output devices, terminal equipment, etc., abnormalities in program execution are monitored based on a clock mechanism. This monitors the program execution time using a control program of an electronic computer, and FIG. 3 shows an example of the configuration of a general clock mechanism.

In Fig. 3, 1 is a standard timekeeping reference pulse generator that generates regular periodic standard timekeeping reference pulses that serve as a reference for the clock mechanism, and 2 is a clock counter that counts the timekeeping reference pulses to express the reference time of the electronic computer. It consists of a counter with several tens of digits.

The clock counter 2 records the elapsed time from the start of counting by counting the reference pulses from the time reference pulse generator 1, and sends the elapsed time to the central processing unit of the electronic computer. .

The central processing unit then learns the program execution time from the elapsed time and monitors the program execution. At this time, the clock counter 2 continues to count the time reference pulses and sends them to the central processing unit while the computer is powered on, regardless of the operating status of the computer.

[Problem to be solved by the invention]

As described above, in the conventional clock mechanism control method for electronic computers, the counting of time reference pulses is maintained regardless of the operating status of the electronic computer. If it stops,
During this time, the timing reference pulses are still being counted, so when the abnormality is removed and program execution resumes, the program execution time may exceed the monitoring time, and this will be treated as an abnormality, which will interfere with program execution. There is also a problem that the representation value of the clock counter is greatly different from the actual time.

This invention was made in order to solve these problems, and the execution of the program is not affected by the abnormal processing time of the computer, and the value of the clock counter does not differ from the real time. The purpose is to provide a clock mechanism control method.

(Means for Solving Three Problems) A clock mechanism control method according to the present invention includes a plurality of reference pulse generators that generate reference pulses with different periods, and a plurality of counters that count the reference pulses and express time. When one of the counters counting reference pulses of the same period stops counting the reference pulses, the other counter continues counting the reference pulses and stops counting. When one counter restarts counting, the counter is switched to supply a reference pulse with a shorter period than H, and the counted value of this one counter is the counted value of the other counter that continued counting. When the same value is reached, the counter is switched to supply a reference pulse having the same original cycle as the other counter, which restarts counting.

[Effect]

In the clock mechanism control method of this invention, when one of the counters that counts the same reference pulse stops, the other counter continues counting the reference pulse, and synchronizes when one counter resumes counting. The short reference pulse of the counter is counted, and the original reference pulse is counted when the count value of the other counter reaches the same value, so the program execution time does not exceed the monitoring time, and the clock There is no difference between the counter value and the actual time.

(Example) Hereinafter, an example of the present invention will be described based on FIGS. 1 and 2.

FIG. 1 is a configuration diagram of a clock mechanism of an electronic computer according to the present invention, and in the figure, 1 is a standard timekeeping reference pulse generator that generates a standard timekeeping reference pulse 2 (S-CLK) that is the reference of the clock mechanism. , 2 is a clock counter (T
OD CTR), 3 is a high-speed timekeeping reference pulse generator used when the clock counter 2 stops, and generates a high-speed timekeeping reference pulse (F-
CLK).

4 is a backup counter (BACK UP) that always counts the timing pulses from the standard timing reference pulse generator 1.
(:Tn), 5 stops the supply of time reference pulses during computer hardware abnormality processing or from the time the abnormality processing is completed until the count value of clock counter 2 reaches the same value as the count value of backup counter 4. 6 is a comparator that compares the values of the clock counter 2 and the backup counter 4, and 7 is a hardware abnormality processing start signal (T-TOD) given to the clock mechanism from the outside. 8 is a latch (CTR-CTL) that controls the supply of the standard timekeeping reference pulse to the clock counter 2;
I), 9 is an inverting gate that inverts the output of latch 8, 10
11 is an inversion gate that inverts the hardware abnormality processing end signal (-END to MC) given from the outside to the clock mechanism; 11 is a latch (CTR-CTL2) that controls the supply of high-speed time reference pulses to the clock counter 2; Like the latch 8, it is composed of a flip-flop.

12 is an inverting gate that inverts the coincidence signal (CTR-HQ) from the comparator 6;

Next, the operation will be explained using the timing chart shown in FIG.

Figure 2 shows the above-mentioned signals, switching gate 5, and latches 8 and 1.
1 shows the output waveform of No. 1.

In a normal state, both the clock counter 2 and the backup counter 4 count the same synchronized time reference pulses from the standard time reference pulse generator 1, and the contents of both counters have the same value. In this state, both the latch 8 and the latch 11 are in the reset state.

Here, when a hardware abnormality occurs in the computer and the service processor starts abnormality processing, a signal to start processing the hardware abnormality is inputted manually, and the latch 8 is set to the set state by the output from the inversion gate 7. The supply of the standard timing reference pulse to the counter 2 is cut off by the timing pulse switching gate 5, and the timing counter 2 is stopped.

However, during this time, the other backup counter 4 is supplied with the timing pulse from the standard timing reference pulse generator 1, and continues its timing operation. At this time, the coincidence signal output from the comparator 6 becomes insignificant because a difference occurs between the two counter values due to the stoppage F of the time counter 2.

When the above-mentioned service processor completes the abnormality processing and a hardware abnormality processing end signal is input manually, the latch 11 is set to a set state by the output from the inversion gate 10, and the high-speed time reference pulse from the high-speed time reference pulse generator 3 is output. is supplied to the clock counter 2 via the clock pulse switching gate 5. The synchronization of the pulses generated by the high-speed timekeeping reference pulse generator 3 is slightly shorter than the synchronization of the pulses generated by the standard timekeeping reference pulse generator 1, so that the count value of the clock counter 2 gradually approaches the count value of the backup counter 4. When the values of both hands of the clock counter 2 and the backup counter 4 reach the same value, the coincidence signal from the comparator 6 becomes significant, and the output from the inverting gate 12 causes the latch 8 and the latch 11 to be reset. The system returns to the state before the hardware error occurred. That is, by resetting the latch 8 and the latch 11, the timekeeping reference pulse supplied to the clock counter 2 is switched to the original standard timekeeping reference pulse from the standard timekeeping reference pulse generator 1, and the timekeeping operation with the same value as the backup counter 4 is performed. Return.

In this way, when one of the counters counting standard time reference pulses of the same synchronization stops counting, the other backup counter 4 is made to continue counting while the other counter 2 is kept counting. When restarting counting, a high-speed timekeeping reference pulse with slightly shorter synchronization than before is supplied, and when the count value becomes the same as the count value of the backup counter, the original standard timekeeping reference pulse is supplied. Therefore, even if abnormal processing is executed for a long time by a slow service processor,
A program being executed on a computer is not affected by program execution time monitoring, and even after a hardware abnormality occurs in the computer, the count value of the clock counter 2 can be restored to the real time in a relatively short time.

Especially recently, the central processing units of electronic computers have become faster,
Although the processing speed difference between the service processing device and the service processing device has increased significantly, it is possible to set an appropriate monitoring time even in such a case, and furthermore, in cases where the slow service processing device needs to intervene due to a computer hardware abnormality. Even in this case, when the retry is successful, the monitoring time of the control program is not exceeded, and the time on the computer can be made practically no different from the real time.

In the above embodiment, two types of timekeeping reference pulse generators are provided separately, but a format may be adopted in which the frequency of the reference pulse from one type of reference pulse generator is divided to supply a plurality of timekeeping reference pulses. .

〔Effect of the invention〕

As described above, according to the present invention, when one counter stops counting reference pulses, the other counter continues counting, and when one counter resumes counting, a reference pulse with a shorter period than before is supplied. However, since the original reference pulse is supplied when the same count value as the other counter is reached, even if a hardware error occurs in the computer, it will not be treated as a program execution error, and the program will continue to run. It is possible to obtain the effect that the clock counter is not affected by the abnormality processing time, and the count value of the clock counter does not differ from the actual time.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a clock mechanism according to an embodiment of the present invention.
Figure 2 is a timing diagram showing the operation of the clock mechanism in Figure 1;
FIG. 3 is a configuration diagram of a conventional clock mechanism. 1...Standard timing reference pulse generator 2------
-Clock counter 3-----High-speed time reference pulse generator 4...
・Hookup counter 5... Timing pulse switching gate 6... Comparator 8.11... Latch. Note that the same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

[Claims] It is equipped with a plurality of reference pulse generators that generate reference pulses with different periods, and a plurality of counters that count the reference pulses to express time. When a counter stops counting reference pulses, the other counter continues counting reference pulses, and when the counter that stopped counting resumes counting, it uses a reference pulse with a shorter period than before. When the count value of one counter reaches the same value as the count value of the other counter that continued the counting, the other counter is switched to the one counter that restarted the counting. A clock mechanism control method characterized by switching to supply a reference pulse with the same original period as the clock mechanism.