JPH10228397A - Watchdog timer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a watchdog timer possible to freely set up the time up to time-out from the external and can be stopped from the external. SOLUTION: When a PRT input and an EN input are at high levels, a counter 1 to be an 8-bit counter is returned to '0' after counting up 0 to 255. When 8Eh is set up in a time-out value setting latch 2, a WDT time-out signal is outputted from a comparator 3 when the counter 1 becomes 8Eh. When 00h is set up in the latch 2, a decoder 5 outputs a low level independently of the state of a WDT stop input terminal 4 and stops the counter 1. When the terminal 4 is connected to a low level in order to execute the debugging or the like of a program, the counter 1 can be stopped independently of the output of the decoder 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a watchdog timer, and more particularly to a watchdog timer with a software stop function for monitoring runaway of a CPU.

[0002]

2. Description of the Related Art A watchdog timer (WDT) is a type of timer that counts clocks and monitors the passage of time.
If the computer program is running properly,
U generates a program reset signal (PRT) and resets the watchdog timer, for example, every 5.12 seconds. If the CPU stops or goes into an abnormal state such as runaway, the program reset signal (PRT) is not generated.
The watchdog timer keeps counting and, for example, when 7.68 seconds elapse, a timeout occurs and an alarm is issued for the CPU abnormality.

[0003] Today, the CPU is at the center of all systems and control means, and the time intervals for monitoring abnormal conditions such as stoppage and runaway also differ depending on the purpose of the system and control. Therefore, it is necessary to watch various time intervals of various CPU control systems.

Japanese Patent Laid-Open Publication No. Hei 5-61725 proposes a watchdog timer circuit as shown in FIG.
3, a decoder 11 for converting input time information T into count information CD, and a timer circuit 12 for counting a corresponding time according to the count information CD of the decoder 11 are provided.
The time information T can be set from outside. Preferably, the count information CD is preset number information for a counter circuit or frequency division number information for a frequency division circuit.

When the program reset signal (PRT) does not arrive, the timer circuit 12 counts clocks up to the number (time elapsed) determined by the count information CD and issues time-out information (CPU alarm).

[0006]

For example, during debugging of software (program), it is necessary to stop the watchdog timer. In the case of the proposal described in Japanese Patent Application Laid-Open No. Hei 5-61725, the elapse of time until timeout can be freely set from the outside, but there remains a problem that the watchdog timer cannot be stopped.

[0007] It is an object of the present invention to provide a watchdog timer in which the time elapsed until timeout can be set freely from the outside and can be stopped from the outside.

[0008]

According to the present invention, an abnormality such as a runaway of a CPU according to the present invention is monitored, and when a computer program is operating normally, a reset operation is performed by a program reset signal and a predetermined timeout value is reached. Then, a watchdog timer having a clock counter circuit for outputting a time-out signal as an alarm signal is provided with a time-out value setting means for setting the time-out value by externally inputting data, and a count stopping means for stopping the counter circuit. And characterized in that:

Further, the count stop means includes a specific data input means for inputting specific data to the timeout value setting means.

Further, the count stop means includes a terminal ground means for forcibly applying a low level to an enable terminal of the count circuit.

The operation of the present invention is as follows. A time-out value (elapsed time until time-out) setting latch is provided, and an external watchdog timer stop input terminal is provided in the timer circuit (counter).

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a watchdog timer according to the present invention.

In FIG. 1, a watchdog timer according to the present invention is reset when a PST (program reset) input goes low, and stops counting when an EN (enable) terminal goes low (ground).
For example, an 8-bit counter 1 for counting LK (clock), when the CLR (clear) input goes low, the outputs are all set to high (ffh). Timeout value setting latch 2, which is, for example, an 8-bit latch element, for latching bit timeout data (data for setting a desired timeout value from the outside);
The comparator 3 compares the output of the counter 1 with the output of the timeout value setting latch 2 and outputs a high level during a period in which both are equal. The decoder 5 outputs a level.

In the operation of the embodiment of the present invention, when the PRT input and the EN input are set to a high level (non-active), the counter 1 counts up by the input CLK. If the counter 1 is, for example, an 8-bit counter, the counter 1 counts up from 0 to 255 (ffh) and returns to 0.

Now, 255 is set in the timeout value setting latch 2.
If (ffh) is set, the counter 1 is set to 255
, The output of the timeout value setting latch 2 matches the output of the counter 1, and the comparator 3 outputs a high-level pulse (WDT timeout signal) having a width of 1 CLK. In this case, after the PRT signal becomes high level,
The time interval until the WDT timeout signal is output is about 32 μm when the CLK frequency is, for example, 8 MHz.
s.

If 8Eh is set in the timeout setting latch 2, for example, as shown in the timing chart of FIG. 2A, the WDT timeout signal is output when the counter 1 counts up to 8Eh. In this case, the time interval from when the PRT signal goes high to when the WDT timeout signal is output is about 17.75 μs when the CLK frequency is 8 MHz, for example.

Further, 00h is set in the timeout setting latch.
Is set, the decoder 5 outputs a low level. A
Since the ND gate 6 becomes an OR circuit when considered with negative logic,
Regardless of the state of the WDT stop input terminal 4, the counter 1 is stopped by outputting a low level. This state is maintained until the value latched in the timeout setting latch 2 is updated. The timing chart at this time is shown in FIG.
Shown in

Further, for the purpose of, for example, debugging a program (software), the WDT stop input terminal 4
Is connected to a low level (ground), the decoder 5
, The counter 1 can be stopped.

[0020]

As described above, according to the present invention, a watchdog timer is formed by giving a specific value (for example, 00h) as timeout data or by giving a low level (ground) to a WDT stop input terminal. There is an effect that the operation of debugging a program (software) can be performed while stopping the counter and preventing generation of a WDT timeout signal.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart of the embodiment of the present invention.

FIG. 3 is a block diagram illustrating an example of a conventional watchdog timer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Counter 2 Timeout value setting latch 3 Comparator 4 WDT stop input terminal 5 Decoder 6 AND gate

Claims (3)

[Claims] An abnormal condition such as a runaway of a CPU is monitored. When a computer program is operating normally, a reset operation by a program reset signal is received. When a predetermined timeout value is reached, a timeout signal as an alarm signal is issued. A watchdog timer having a clock counter circuit that outputs a clock signal, comprising: a timeout value setting unit configured to set the timeout value by inputting data from outside; and a count stop unit configured to stop the counter circuit. Features a watchdog timer. 2. The watchdog timer according to claim 1, wherein said counting stop means includes specific data input means for inputting specific data to said timeout value setting means. 3. The watchdog timer according to claim 2, wherein said count stop means includes a terminal grounding means for forcibly applying a low level to an enable terminal of said count circuit.