JPH0384640A - Informing system for fault information - Google Patents

Abstract

PURPOSE:To grasp the fault state of one of two processors by reading the coding information stored in a state holding means via the other processor. CONSTITUTION:A processor 3 has a fault and this error information is stored in one of status holding means 301 - 304. Thus a microprocessor 31 of the processor 3 reads the error information out of the means 301 - 304 and codes the information via a code generating means 31A to store this coded information in a state holding means 32. When the coded error information is written into the means 32, this fact is informed to a processor 1 with an interruption signal 4. Thus the processor 1 reads only the error information on the processor 3 out of the means 32. Then the fault state of the processor 3 can be grasped.

Description

[Detailed Description of the Invention] [Summary] In a multiprocessor system consisting of a plurality of processors, the amount of hardware is increased with respect to a failure information notification method in which a processor in which a failure occurs notifies other processors of failure information. The objective is to provide a failure information notification method that can notify failure status at low cost without having to worry about failures, and can reliably notify even serious failures. In the multiprocessor system, a plurality of status holding means are provided in the processor to store various error information corresponding to error types, and when a failure occurs in one processor, the other processor is notified of the failure. When error information due to failure occurrence is stored in multiple status holding means, this error information is read out and encoded, and when the microprocessor in the processor performs a machine check bolt, a predetermined information corresponding to this state is stored. A code generating means for performing encoded output, and a state holding means for storing the encoded information outputted by the code generating means and outputting an interrupt signal notifying that a failure has occurred are provided. When human power is available, an interrupt signal is issued to notify the other processor, and this notification causes the other processor to grasp the failure status of one processor by reading the encoded information in the state holding means. It was configured as follows.

[Field of Industrial Application] The present invention relates to a fault information notification method in which a processor in which a fault has occurred notifies other processors of fault information in a multiprocessor system composed of a plurality of processors.

In the past, the mainstream of data processing equipment was uniprocessor systems in which a single processor performed all types of data processing, but in recent years there have been concerns about the limits of processing capacity of such uniprocessor systems. Instead, multiprocessor systems in which multiple processors share processing are on the rise.

In such a multiprocessor system, when a failure occurs in a certain processor, it is necessary to reliably notify other processors of the failure information.

[Prior Art] As a conventional failure information notification system, there is one shown in FIG. 11, for example.

In FIG. 11, 1 is a processor on the side that receives notification of a failure, and 3 is a processor on the side where the failure has occurred. These processors 1.3 are connected to each other via a data bus 2 and an address bus 7. There is. The processor 3 includes various status registers, such as a status register 301 that stores MPU-related error information, a status register 302 that stores memory bus-related error information from the bus monitoring circuit 8, and input/output bus-related error information. A status register 303 for storing timer-related error information and a status register 304 for storing timer-related error information are provided. When an error occurs in the processor 3, the status register 301 changes depending on the type of error.
- 304 are set, and the OR circuit 39 outputs an interrupt signal 3A to the microprocessor (MPU) 31 and outputs an interrupt signal 4 to the microprocessor (MPU) 11 of the processor 1.

The MPU 31 of the processor 3 is halted by the interrupt signal 3A, and the MPU II of the processor 1 outputs an address signal to the processor 3 via the tri-state driver 327. This address signal is transmitted to the tri-state driver 32
4 is latched by the address latch 40, and the decoder 4
1, the multiplexer 309 and the multiplexer 311 are activated by the select signal, the error information set in the status registers 301 to 304 is read into the MPU II, and the error type is displayed on the error display device 9. .

Note that 310 is a multiplexer operated by a select signal obtained by decoding the address of MPU 31 by decoder 42, and data from memory and data from other registers are taken into MPU 31. Here, interrupt signal 3
A prevents error information from the status registers 301 to 304 from being taken into the MPU 31 via the multiplexer 310. Further, 320 to 327 each indicate a tri-state driver.

Next, another fault information notification method is shown in FIG.

In FIG. 12, reference numeral 1 denotes a processor receiving notification of a failure, 3 a processor on the side in which a failure has occurred, 2 a data bus connecting processors 1 and 3, and 5 an error information 51 transmitted via the data bus 2. 4 is an interrupt signal notified from the processor 3 to the processor 1.

When a failure occurs on the processor 3 side, the processor 3 writes error information 51 to the common memory 5 via the data bus 2, notifies the processor 1 of the interrupt using the interrupt signal 4, and then halts the process. The error information 51 is then read out by the processor 1.

[Problem to be Solved by the Invention] However, in the conventional failure information notification method, in the former case, the other processor that received the notification registers multiple status registers of the processor that generated the interrupt. must read out the contents. Among them, there are status registers that cannot be read by other processors, and other processors may not be able to obtain accurate information. However, if all the status registers were made readable by other processors, there was a problem in that the amount of hardware required to read the status registers would increase, leading to an increase in cost.

In the latter case, if a failure occurs in the memory access control unit, the failure information cannot be written to the common memory, so there is a problem that the other processor cannot understand the details of the failure of the failed processor. Ta.

The present invention has been made in view of these conventional problems, and is capable of notifying failure conditions at low cost without increasing the amount of hardware, and also being able to reliably notify even serious failures. The purpose of this project is to provide a failure information notification method that can be used.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 1 and 3 are processors, 301 to 304
31A is a status holding means for storing various kinds of error information corresponding to error types in the processor 3; 31A is a means for reading out various kinds of error information stored in the plurality of status holding means 301 to 304 and outputting encoded information; Further, when the microprocessor 31 in the processor 3 performs a machine check, a code generating means 32 performs a predetermined encoded output corresponding to this state, and 32 is the code generating means 31A.
It is a state holding means that stores the encoded information outputted by the controller and also outputs an interrupt signal 4 notifying that a failure has occurred.

[Operation] When a failure occurs in the processor 3 and the error information is stored in any of the status holding means 301 to 304,
The microprocessor 31 in the processor 3 reads error information from the status holding means 301 to 304, and
Code generation means 31. A and stored in the state holding means 32.

When coded error information is written to the status holding means 32, it is notified to the processor (by the interrupt signal 4).Furthermore, when the microprocessor 31 performs a machine check bolt, the corresponding coding is performed. The state is stored in the state holding means 32, and the interrupt signal 4 causes the processor 1 to
will be notified.

The processor 1 that has received the notification can grasp the failure status of the processor 3 by reading only the state holding means 32 of the processor 3.

In this way, fault information can be grasped at low cost without increasing the amount of hardware, and even serious faults can be reliably grasped.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIGS. 2 to 10 are diagrams showing an embodiment of the present invention.

FIG. 3 is a diagram showing the overall system configuration of the present invention.

In FIG. 3, 1 and 3 are processors, and these processors 1 and 3 and a common memory 5A are connected to each other via an address bus 7 and a data bus 2. In FIG. These processors 1 and 3 and common memory 5A constitute a multiprocessor system as a whole. Here, processor 3 is assumed to be the processor in which the failure has occurred, and processor 1 is assumed to be the processor that receives notification of the failure.

A memory bus monitoring circuit 8 is connected to the address bus 7 and the data bus 2, and an error display device 9 is connected to the processor 1.
is connected.

Next, in FIG. 2, 301 to 304 are processors 3
The status register 301 stores MPU-related error information, the status register 302 stores memory bus-related error information, and the status register 303 stores I10 bus-related errors. The status register 304 stores timer-related error information.

As shown in FIG. 5, the status register 301 has 8
For example, MPU address parity error, MPU
Write data parity error, MPU fetch data parity error, MPU read data parity error, M
PU control signal parity error, MPU invalid address detection, MPU undefined control signal detection, and MPU undefined interrupt signal detection are each set.

The status register 302 has 8 registers as shown in FIG.
For example, memory bus address parity error, memory bus write data parity error, memory bus fetch instruction parity error, memory bus read data parity error, memory bus control signal parity error, Memory bus address over, memory bus undefined control signal detected, and memory uncollector pull error are each set.

The status register 303 has 8 bits as shown in FIG.
For example, I10 bus address parity error I1
0 Bus write data parity error I10 Bus undefined write data detected, I10 Bus read data parity error 110 Bus control signal parity error I1
0 bus invalid address detection, I10 bus undefined control signal detection, and I10 bus priority error are each set.

As shown in FIG.
It is composed of J flip-flops 3040 to 3047, for example, MPU fetch instruction timeout, MPU
Read data timeout, memory bus fetch instruction timeout, memory bus read data timeout, I
10 path read data timeout, MPU timer abnormality, memory bus monitoring timer abnormality, and I10 bus monitoring timer abnormality are each set.

The holding states (0, 1) of the flip-flops in each J- of these status registers 301 to 304 occur in the combination shown in FIG.

Each error information set in status registers 301 to 304 is output to OR circuit 39 and multiplexer 310, respectively.

The OR circuit 39 outputs the MPU interrupt signal 3A to the microprocessor (MPU) 31, and the MPU 31 sends the error information in the status registers 301 to 304 to the multiplexer 3.
10. That is, M from the MPU 31
The address signal via the PU address bus 37 is decoded by the decoder 42 and input to the multiplexer 3 (0), and the data selected by the multiplexer 310 is read into the MPU 31 via the MPU data bus 33.

Note that data from the common memory 5A and data from other registers are also input to the multiplexer 310 via the data bus.

The MPU 31 stores fault information in the status registers 301 to 301.
When the fault is of the type stored in the MPU 304, a code corresponding to the fault is generated by reading the stored value.However, when a fault occurs due to the MPU 31 itself, the machine enters a machine check bolt state, and this The code corresponding to (
A machine check bolt signal 34) is generated (see the bottom row of FIG. 4). Therefore, the MPU 31 also functions as a code generating means 31A that generates codes corresponding to the error information and machine check bolt states stored in the status registers 301 to 304.

32 is a status register as status storage means, and the status register 32 includes status registers 301 to 304.
The encoded error information read from and encoded machine check voltage signals are stored. Note that, herein, these error information and machine check bolt signals are referred to as failure information. The status register 32 includes eight J- flip-flops 3200 to 3, as shown in FIG.
The machine check voltage signal 34 is stored in the J-flip-flop 3200, and coded error information is stored in the other J-flip-flops 3201 to 3207. The fault information stored in status register 32 is transmitted to multiplexer 309 and OR circuit 34.
0 respectively.

The interrupt signal 4 is sent from the OR circuit 340 to the MP of the processor 1.
Based on this interrupt signal 4, the MPU II outputs the address signal of the status register 32 to the address latch 40 via the address bus 7.

40 is an address latch in which an address signal from the processor 1 is latched, and the output of the address latch 40 operates the multiplexer 309.

The fault information in the status register 32 is read from the multiplexer 309 via the data bus 2 to the MPU II in the processor 1 .

The fault information from the status register 32 is taken into the MPU II, and the error display device 9 displays the type of fault. Note that 320 to 323 degrees and 325 to 330 are tristate drivers.

Next, the operation will be explained.

FIG. 10 shows a flowchart for processing fault information.

In FIG. 10, when an error occurs, step S1
The error information is stored in the status registers 30-304. The outputs of the status registers 301 to 304 are given to an OR circuit 39, and the OR circuit 39 outputs an MPU interrupt signal 3A to the MPU 31. In this way, the interrupt processing routine is entered from the normal processing, and the status register 301 is read in step S2. Next, if all the values in the status register 301 are zero in step S3, the process advances to step S4, and if they are not zero, the process advances to step S9.

Read the status register 302 in step S4,
If all the values in the status register 302 are zero in step S5, the process advances to step S6, and if they are not zero, the process advances to step S9.

Read the status register 303 in step S6,
If all the values in the status register 303 are zero in step S7, the process advances to step S8, and if they are not zero, the process advances to step S9.

In step S8, the status register 304 is read, but in this case, an error corresponding to the status register 304 has occurred, so all values in the status register 304 are not zero. In step S9, the MP
U31 generates an error code based on FIG.

Also, when a machine check bolt occurs, an error code corresponding to the machine check bolt signal 34 is generated based on FIG. 4.

For example, when an MPU fetch data parity error occurs, an error signal is input to the "J" terminal of the flip-flop 3012 to J- of the status register 301 in FIG. The third bit from the top becomes "1", and the value encoded accordingly becomes "00011110" as shown in the "Stored value column to status register 32" in the same figure, and in the case of an I10 bus address parity error. "J" of the flip-flop 3030 is connected to J- of the status register 303 in FIG.
An error signal is input to the terminal, and the first bit from the top of the ``status register 303 column'' in Figure 4 becomes 1'', and the encoded value corresponding to this becomes 1''.
When the microprocessor 32 performs a machine check, it becomes "1oooooooo" as shown in the "value field stored in the status register 32" in FIG.

Next, in step S10, the coded failure information is written into the status register 32, and the MPU 31 is halted. When the fault information is set in the status register 32, the OR circuit 340 outputs interrupt signal 4 to MPULL, and the MPU
11 outputs the address signal of the status register 32 from the tri-state driver 327 in response to the interrupt signal 4,
As described above, the multiplexer 309 is activated by the output from the address latch 40, and the status register 32 is read via the data bus 2 (see step S12). The failure information is then displayed on the error display device 9 in step S13.

In this way, when a failure occurs in processor 3,
The processor 1 that receives the notification only needs to read out the two status registers 32, so there is no need for a circuit to read out all the registers on the faulty side, and the amount of hardware can be reduced. Further, when adding a status register, conventionally the amount of hardware increases significantly, but in this embodiment, the amount of hardware does not need to be increased. In addition, even if MPU3↑ causes a machine checkvolt due to a serious failure such as not being able to read or write to the register of processor 3, simply setting the machine checkvolt signal 34 to the status register 32 will ensure that the serious failure occurs in processor 1. can be grasped.

[Effects of the Invention] As explained above, according to the present invention, when a failure occurs in a processor configured in a multi-system,
Other processors only need to read one status register on the faulty side, so there is no need to increase the amount of hardware.
Failures can be detected at low cost. Also, MPU
Even when a machine is checked due to a serious fault in which the processor cannot read or write registers, it is possible to reliably detect the serious fault as a multi-system.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a diagram showing an embodiment of the present invention, Fig. 3 is an overall configuration diagram of the present invention, Fig. 4 is a diagram showing the values of each register, Fig. 5 6 is a configuration diagram of the status register 301, FIG. 7 is a configuration diagram of the status register 303, FIG. 8 is a configuration diagram of the status register 304, and FIG. 9 is a configuration diagram of the status register 32. FIG. 10 is a flowchart, FIG. 11 is a diagram showing a conventional example, and FIG. 12 is a diagram showing another conventional example. In the figure, 1.3...Processor, 2...Data bus, 4...Interrupt signal, 31...Microprocessor, 31A...Code generation means, 32...Status register (state retention) means), 301-3
04...Status register (status holding means)

Claims (1)

[Claims] A plurality of status holding means (301 to 301) storing various error information corresponding to error types in a plurality of processors (1) and (3) connected to each other via a bus (2). 3
04), in which when a failure occurs in one processor (3), the other processor (1) is notified of the failure. When error information associated with this state is stored, this error information is read out and encoded, and when the microprocessor (31) in the processor (3) performs a machine check bolt, a predetermined encoding corresponding to this state is executed. A code generation means (31A) for outputting, and an interrupt signal (31A) for storing the encoded information outputted by the code generation means (31A) and notifying that a failure has occurred.
A state holding means (32) is provided which outputs the state holding means (32), and when there is an input to the state holding means (32), an interrupt signal (4) is provided.
is issued to notify the other processor (1), and this notification causes the other processor (1) to update the state holding means (32).
) A failure information notification method is characterized in that the failure status of one processor (3) can be grasped by reading the encoded information within ).