JPH05120153A - Alternate memory control system - Google Patents

Abstract

PURPOSE:To automatically, and alternately process and a defective memory printed board with the non-defective one even in an operating state of a device if a 1-bit error occurs in an alternate memory control system. CONSTITUTION:When an error detecting part 3A detects the 1-bit errors of the memory printed boards 9-1 and 9-2, an alternate memory printed board 17 is selected with an alternation control part 12 and a printed board selecting part 16. Then the contents of the memory printed board having a 1-bit error are copied to the board 17 under the control of a memory control part 18. The board 17 is validated by the selection carried out through the part 12 and the printed board selecting parts 14, 15 and 16. Then the defective printed board is isolated and replaced with the non-defective one while an access is temporarily stopped by an instruction of an access stop instruction part 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a device provided with a memory array composed of a plurality of semiconductor memory mounted printed boards, such as a semiconductor disk device, and in particular, it is used for a semiconductor memory mounted printed board unit. The present invention relates to a replacement memory control system for performing replacement.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional semiconductor disk device, in which 1 is an interface control unit, 2 is a memory access circuit, 3 is an error detection circuit, 4 is a status register, and 5 is an MPU ( Microprocessor, 6 is a control memory, 7 is an address decoder, 8 is a memory array, 9
Reference numerals -1, 9-2 denote a memory printed board, 10 a semiconductor disk control device, and 11 a semiconductor disk device.

Conventionally, a semiconductor disk device has been developed as an external storage device of a computer system. This semiconductor disk device is a device that uses a semiconductor memory as a storage medium and virtually executes the input / output processing of the magnetic disk device.

That is, the semiconductor disk device itself is controlled by the host system as a magnetic disk device having a small storage capacity, and has a relatively small capacity.
It was developed as a device that absolutely evaluates the speed of access response.

The semiconductor disk device is constructed, for example, as shown in FIG. In this example, the semiconductor disk device 11 includes an interface control unit 1, a memory access circuit 2, an error detection circuit 3, a status register 4, and an MPU.
5, a control memory 6, an address decoder 7, and a memory array 8 are provided, and the semiconductor disk device 11 is connected to the semiconductor disk control device 1 via a memory interface.
Connect to 0.

The memory array 8 is provided with memory printed boards 9-1 and 9-2. In this example, 2
Although the memory array 8 is composed of the memory printed boards, more memory printed boards are actually provided.

The memory printed boards 9-1, 9-2 are
In each case, a semiconductor memory is mounted on the printed circuit board (only the semiconductor memory is mounted). The memory printed boards 9-1 and 9-2 are configured to be attachable to and detachable from the printed board storage cage in units of memory printed boards.

In the semiconductor disk device 11 having the above structure, the memory printed boards 9-1, 9- of the memory array 8 are arranged.
At 2, data is read / written from the semiconductor disk control device 10 via the memory access circuit 2.

The memory access circuit 2 generates a timing signal for accessing the memory printed boards 9-1, 9-2 and automatically corrects a 1-bit error (adds ECC). Further, an error during memory access is performed by the error detection circuit 3, and the result is stored in the status register 4.

The address decoder 7 decodes the upper bits of the address signal sent from the memory access circuit 2 and outputs a selection signal for selecting the memory printed board to the memory array 8.

The memory printed board selected by the signal is accessed through a common memory bus to read / write data. In addition to such data read / write, the MPU 5 performs patrol diagnosis.

In this patrol diagnosis, each memory printed board is accessed and data is read under the control of the MPU 5, and at this time, the error detection circuit 3 detects an error. Then, the error detection result is displayed in the status register 4
To store.

The contents of the status register 4 are read by the MPU 5, and if there is an error, it is notified to the host device of a higher level via the upper semiconductor disk control device 10. The host device that has received this notification notifies the maintenance personnel and the like by means of a display or the like.

[0014]

SUMMARY OF THE INVENTION The above-mentioned conventional device has the following problems. (1) In the conventional memory array, ECC (error correction code) is added to a memory error to automatically correct a 1-bit error. For this reason, even if a 1-bit error occurs, the defective memory printed board is replaced as it is when it is used as it is and when the use of the apparatus is finished (for example, at night).

However, among the recent information processing devices, 24
The number of time-operated devices is increasing. In such a usage environment, the device in use must be stopped in order to secure a time to replace the memory printed circuit board in which the 1-bit error of the memory has occurred. Therefore, the reliability and maintainability of the device are reduced.

(2) In order to solve the above problem (1),
It has also been considered to perform alternation processing of memory elements inside the memory printed board. However, with such a method, although the 1-bit error can be avoided, the printed board is not replaced, and the apparatus is continuously used in a problematic state.

Therefore, also in this case, the reliability and maintainability of the apparatus are deteriorated. The present invention solves such a conventional problem, and when a 1-bit error occurs in the memory printed board, the defective memory printed board is automatically replaced, and the defective memory printed board is operated during the operation of the device. The purpose is to be able to exchange for good products.

[0018]

FIG. 1 is a principle view of the present invention. In the figure, the same reference numerals as those in FIG. 3 indicate the same elements. Also,
2A is a memory access unit, 3A is an error detection unit, 7A is an address decoder unit, 11 is a memory control unit, 12 is a replacement control unit, 13 is an access stop instruction unit, 14 to 16 are printed circuit board selection units, and 17 is a replacement memory unit. A printed board is shown.

In order to solve the above problems, the present invention has the following configuration. (1) Multiple memory printed boards 9 equipped with semiconductor memory
-1, 9-2, a memory access section 2A for connecting and accessing a plurality of memory printed boards 9-1, 9-2, and a memory control section for performing various controls on the memory printed boards 18, an address decoding unit 7A that generates selection information for selecting a memory printed board based on the address information output from the memory access unit 2A, and an error detection unit 3A that detects an error during memory access. A function to automatically correct a 1-bit error in the semiconductor memory (addition of ECC)
An alternate memory control system for an apparatus comprising: an alternate memory printed board 17 for replacing an error-occurring memory printed board in the memory array; And a printed board selection section 14 and 15 for selecting the respective memory printed boards by inputting the output of the address decoding section 7A and the selection prohibition signal of the replacement control section 12.
A printed circuit board selection unit 16 for validating the alternative memory printed circuit board 17 by inputting the output of the address decoding unit 7A, the alternative memory printed circuit board selection signal output from the replacement control unit 12, and the alternate memory printed circuit board valid signal. When the error detection unit 3A detects a 1-bit error of the memory print board, the memory control unit 18 selects the memory print board that detected the 1-bit error only at the time of data writing, and at the same time, the replacement memory. By notifying the replacement control unit 12 that the signal for selecting the printed board is output, the printed board selection unit 16 selects the replacement memory printed board, and then the memory control unit 18 outputs a 1-bit error. Repeated reading and writing of data for all memory areas of the detected memory printed circuit board. The data in the memory of the reprint board is copied to the replacement memory print board 17, and after the copying is completed, the memory control unit 18 detects a 1-bit error via the replacement control unit 12 and the print board selection unit 16. Instead of the printed board, the replacement memory printed board 17 is made effective, and the replacement controller 12 and the printed board selector 14 are provided.
Alternatively, the memory printed board in which the 1-bit error has occurred is disconnected via 15 or 15.

(2) In the configuration (1), the device is provided with an access stop instruction unit 13, and the memory control unit 18 makes a memory access to the memory access unit 2A in response to a request from the access stop instruction unit 13. A stop instruction was issued for a certain period of time, during which a memory printed board in which a 1-bit error occurred could be replaced.

[0021]

The operation of the present invention based on the above construction will be described with reference to FIG. When the error detection unit 3A detects a 1-bit error in the memory print board, the memory control unit 18 selects the replacement memory print board at the same time when the memory print board that has detected the 1-bit error is selected only when data is written. The switching control unit 12 is notified that a signal for outputting is used, and the printed board selection unit 16 or the replacement memory printed board 17 is selected.

After that, the memory control section 18 repeats reading and writing of data for the entire area of the memory of the memory printed board in which the 1-bit error is detected, so that the memory printed board in which the 1-bit error occurs is stored. Existing data is copied to the alternate memory printed board 17.

When the copying is completed, the memory controller 18
In order to enable the replacement memory printed board 17 in place of the memory printed board which detected the 1-bit error,
The replacement memory printed board 17 is validated via the replacement control section 12 and the printed board selection section 16.

At the same time, in order to separate the memory printed board on which the 1-bit error is detected, the memory printed board on which the 1-bit error is detected is cut off via the alternation control section 12 and the printed board selection section 14 or 15. ..

When the memory printed board in which the 1-bit error has occurred is replaced with a good one, the access stop instruction section 13
Issues an access stop request to the memory control unit 18. In response to this request, the memory control unit 18 issues a memory access stop instruction to the memory access unit 2A for a certain period of time.

Then, the memory printed board in which the 1-bit error has occurred is replaced during the fixed time. In this way, it is possible to perform the replacement process of the memory printed board in which the 1-bit error has occurred, without interrupting the memory access from the host device.

Although the memory access is stopped for a short time when the defective memory printed board is replaced with a good one,
It can be replaced in a very short time while the device is in operation.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a configuration diagram of a semiconductor disk device according to an embodiment of the present invention.

In the figure, the same symbols as those in FIGS. 1 and 3 indicate the same components. Further, 18 and 19 are NOT circuits, 20 and 23 are selection circuits, 21 and 22 are AND circuits, and 24 is a memory printed board insertion / removal detection circuit.

This embodiment is an example applied to a semiconductor disk device, and its configuration is shown in FIG. As shown,
The semiconductor disk device includes an interface control unit 1,
Memory access circuit 2, error detection circuit 3, status registers 4, 17, MPU (microprocessor) 5, control memory 6, address decoder 7, memory array 8, NOT
Circuits 18 and 19, selection circuits 20 and 23, AND circuit 2
1, 22, a memory printed board insertion / extraction detection circuit 24, and a control register 16 are provided.

The memory array 8 also includes memory printed boards 9-1 and 9-2 and a replacement memory printed board 1.
7 is provided. The memory printed board has a semiconductor memory mounted on a printed board and is inserted into a predetermined connector in the memory array 8.

Like the memory printed boards 9-1 and 9-2, the replacement memory printed board 17 has a semiconductor memory mounted on a printed board, and the memory printed boards 9-1 and 9-2 have an error. Is used as a replacement memory in the case of occurrence of.

The memory access circuit 2 is connected to an upper semiconductor disk control device through a memory interface and generates a timing signal for accessing the memory in the memory array 8. Further, the memory access circuit 2 is provided with a circuit for automatically correcting a 1-bit error.

The address decoder 7 decodes the upper bits of the address on the basis of the address information output from the memory access circuit 2 and selects a memory printed board from a plurality of memory printed boards. (Selection signal) is output.

The error detection circuit 3 is a circuit for detecting an error (for example, 1-bit error) of the memory printed board and storing the result in the status register 4. The MPU (microprocessor) 5 is a processor that performs various controls on the memory array 8.

The control memory 6 is a memory used by the MPU 5, and the control register 16 is a register in which information is set by the MPU 5. The operation of the semiconductor disk device in this embodiment will be described below.

Each memory printed board (printed board on which a semiconductor memory is mounted) 9-provided in the memory array 8
1, 9-2 are read / written from the memory interface via the memory access circuit 2. Then, when an error occurs during memory access, this error is detected by the error detection circuit 3, and the information of the detection result is stored in the status register 4.

In this case, an ECC (error correction code) is added in the memory access circuit 2 to the memory error (1 bit error) of the memory printed board, and 1
Automatically correct bit errors.

The address signal input to the memory access circuit 2 is input to the address decoder 7 and becomes a signal for selecting the memory printed board 9-1 or the memory printed board 9-2. This selection signal is supplied to the AND circuit 21,
Alternatively, it is connected to the memory printed board in the memory array 8 via the AND circuit 22.

Further, the memory access circuit 2 outputs a signal necessary for accessing the memory printed board as a common signal to all the memory printed boards. That is, the printed circuit board selected by the memory printed circuit board selection signal performs the read / write operation using the common signal line.

On the other hand, the memory printed boards 9-1, 9-2
Under the control of the MPU 5, the patrol diagnosis is executed. This patrol diagnosis is executed by issuing a read command to the memory access circuit 2 via the control register 16 under the control of the MPU 5, and receiving the result by the status register 4.

Next, the replacement process of the memory printed board when a 1-bit error occurs in the memory of the memory printed board will be described. For example, when a read command is issued to the memory printed board 9-2 through the memory interface, the memory access circuit 2 issues the designated address to the memory printed board. The high-order signal (high-order bit) of this address and the signal of the read command are input to the address decoder 7 to generate a signal for selecting the memory printed board 9-2.

This signal is input to one input terminal of the AND circuit 22. The output signal of the NOT circuit 19 is input to the other input terminal of the AND circuit 22.
Normally, since the output signal of the control register 16 input to the NOT circuit 19 is "0", the two input signals of the AND circuit 22 are "1". As a result, the output signal of the AND circuit 22 becomes "1", and this signal is the memory printed board 9
It is input to the memory printed board 9-2 as a signal for selecting -2.

By the signal output from the AND circuit 22 and the signal output from the memory access circuit 2,
The data of the specified address is read from the memory printed board 9-2, and the data is read by the memory access circuit 2
Output to.

By this operation, the memory access circuit 2
Receives the data of the designated address from the memory printed board 9-2, notifies the address decoder 7 that the read command is completed, and ends the read operation.

At this time, the data received by the memory access circuit 2 is checked by the error detection circuit 3,
When a 1-bit error is detected, error information (error content and location) is stored in the status register 4. MPU
Normally, 5 executes the patrol diagnosis, but when 1-bit error information is detected in the status register 4, the following processing is started based on the information stored in the status register 4.

The MPU 5 stores information in the control register 16 so that the alternate memory print board 17 and the memory print board 9-2 are simultaneously selected at the time of the write operation to the memory of the memory print board. Based on this information, the selection circuit 20 outputs a selection signal for the memory printed board 9-2, and the selection circuit 23 outputs a signal for selecting the alternate memory printed board 17 only at the time of writing.

After that, the MPU 5 issues an instruction (Read & Write instruction) for continuously executing read and write via the control register 16 in order from the first address of the memory printed board 9-2 to the last. Issue up to the address.

By this processing, the data read from the memory printed board 9-2 at the time of reading is written in the memories of both the memory printed board 9-2 and the alternate memory printed board 17 by the subsequent writing. Further, during this processing, the data according to the write command issued from the memory interface is simultaneously written to the memory printed board 9-2 and the alternate memory printed board 17.

When the above processing is completed, the MPU 5 sets the information in the control register 16 in order to replace the functions of the memory print board 9-2 and the replacement memory print board 17. This causes NOT from the control register 16
"1" is output to the circuit 19 and the signal for selecting the memory printed board 9-2 is not output from the output of the AND circuit 22.

At the same time, according to the output signal of the control register 16, the selection circuit 20 causes the replacement memory printed board 1
The selection circuit 23 outputs the selection signal No. 7 and the selection circuit 23 outputs the signal for selecting the alternate memory printed board 17 at the time of writing and reading.

With these processes, the memory print board 17 for substitution operates instead of the memory print board 9-2 for the subsequent memory access. Ie 1
The process of replacing the memory printed board 9-2 in which the bit error has occurred with the replacement memory printed board 17 is completed.

Next, the defective memory printed board 9-2
The case of exchanging is explained. When the above process is completed, the MPU 5 notifies the memory access circuit 2 via the control register 16 that the memory printed board is defective. As a result, the memory access circuit 2 notifies the host device of this information through the memory interface.

Further, when the memory printed board 9-2 is started to be replaced by the above information and the memory printed board 9-2 is pulled out from the printed board storage cage by a maintenance person or the like, the memory printed board insertion / removal detection circuit 24 causes the memory printed board 9-2 to detect the memory. The insertion / extraction of the printed board is detected and the status register 17 is notified.

The MPU 5 detects this state and instructs the memory access circuit 2 via the control register 16 to stop the memory access for a certain period of time. This processing prevents the memory access operation from becoming abnormal due to noise generated when the memory printed board 9-2 is pulled out.

Further, the same processing is executed when a non-defective memory printed board which is to be inserted instead of the memory printed board 9-2 is subsequently inserted so that the memory access is not adversely affected.

(Other Embodiments) The embodiments have been described above, but the present invention can be implemented as follows. (1) When the memory printed board in which an error has occurred is replaced with a non-defective product, in the above embodiment, the memory access is stopped by detecting the insertion / extraction of the memory printed board. The memory access may be stopped for a certain period of time by an instruction such as the above.

(2) The invention is not limited to the semiconductor disk device, but can be applied to various devices provided with a memory array composed of a plurality of memory printed boards (printed boards on which semiconductor memories are mounted).

[0059]

As described above, the present invention has the following effects. (1) Even in an environment where a device equipped with a memory array is continuously used, replacement processing of a defective memory printed board in which a 1-bit error has occurred can be automatically performed.

(2) The replacement process of the memory printed board can be executed without relaying the memory access from the host device. Therefore, the reliability and maintainability of the device can be improved.

(3) The memory printed circuit board in which the 1-bit error has occurred can be replaced with a non-defective product during the operation of the apparatus after the replacement processing for the replacement memory printed circuit board is completed.

In this case, the memory access from the host device is temporarily stopped, but the time is extremely short.
Therefore, also in this respect, the reliability and maintainability of the device are improved.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of a semiconductor disk device according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of a conventional semiconductor disk device.

[Explanation of symbols]

 2A memory access section 3A error detection section 7A address decoding section 9-1, 9-2 memory printed board 12 replacement control section 13 access stop instruction section 14, 15, 16 printed board selection section 17 replacement memory printed board 18 memory control section

Claims (2)

[Claims] 1. A memory array comprising a plurality of memory printed boards (9-1, 9-2) mounted with a memory, and a memory for connecting and accessing the plurality of memory printed boards (9-1, 9-2). An access unit (2A), a memory control unit (18) that performs various controls on the memory printed board, and a memory printed board based on address information output from the memory access unit (2A). An address decoding unit (7A) that generates selection information and an error detection unit (3) that detects an error during memory access.
An alternate memory control method for a device, comprising: A) and a function (ECC addition) for automatically correcting a 1-bit error in the memory, wherein a memory print in which an error occurs in the memory array. Replacement memory printed boards for altering boards (17)
And a replacement controller (12) for controlling the replacement of the memory printed board in the device.
And the output signal of the address decoding unit (7A) and the selection prohibition signal of the alternation control unit (12) to select each memory printed circuit board selection unit (14, 15).
And the output of the address decoding unit (7A) and the alternation control unit (1
The replacement memory printed board selection signal and the replacement memory printed board valid signal output from 2) are input to provide a printed board selection unit (16) for validating the replacement memory printed board (17). When the detection unit (3A) detects a 1-bit error in the memory printed board, the memory control unit (18) selects the memory printed board in which the 1-bit error is detected only when data is written. The printed circuit board selection unit (16) selects the replacement memory printed circuit board by notifying the replacement control unit (12) that a signal for selecting the printed circuit board is output, and then the memory control unit (18) is selected. ) Detected a 1-bit error, repeated reading and writing of data for all memory areas of the memory printed board. The data in the memory of the input board is copied to the replacement memory print board (17), and after the copying is completed, the memory control unit (18) sets the replacement control unit (1).
2) and the printed board selection unit (16), the replacement memory printed board (17) is enabled in place of the printed board in which the 1-bit error is detected, and the replacement control unit (12) and the print An alternate memory control method characterized in that a memory printed board in which a 1-bit error has occurred is separated via a board selecting unit (14 or 15). 2. An access stop instruction unit (1)
3) is provided, and in response to a request from the access stop instruction unit (13), the memory control unit (18) issues a memory access stop instruction to the memory access unit (2A) for a certain period of time. 2. The alternate memory control system according to claim 1, wherein the memory printed board in which the error has occurred is replaceable.