JPH0553618A - Programmable controller - Google Patents

Abstract

PURPOSE:To prevent the destruction of data even when an auxiliary storage device being the peripheral device of a programmable controller is reset in a data fetching state or even when a power supply has the momentary disconnection of power source. CONSTITUTION:A delay circuit 21 is connected to the output side of a reset signal generating circuit 7. The circuit 21 converts a reset signal 101 outputted from the circuit 7 into a delay reset signal 110 that is delayed by a prescribed time. Then the signal 110 is inputted to the control circuit 4 of an auxiliary storage device 5. Thus the reset operation of the circuit 4 is delayed by the delay time of the signal 110. Then the data are continuously written into the storage 5 in the delay time of the reset operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller (hereinafter referred to as a PC) equipped with an auxiliary storage device such as a floppy disk or a hard disk as a peripheral device.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing a concrete configuration of a conventional PC. In the figure, 1 is a microprocessor (hereinafter referred to as CPU), 2 is a ROM which is a memory for storing a program of the PC, Reference numeral 3 is a RAM which is a memory for arithmetic work, 4 is a control circuit which controls each operation of writing and reading to and from the auxiliary storage device 5 which is a floppy disk or a hard disk, and 6 is for connecting the CPU 1 and the control circuit 4 to a PC Interface (hereinafter referred to as I / F). Reference numeral 7 is an externally connected reset signal generating circuit, which includes a molding machine 8, a resistor 9, and a push button switch 10. 10
Reference numeral 1 denotes a reset signal output from the reset signal generation circuit 7.

Next, the operation will be described. CPU1 is R
According to the program stored in the OM 2, the data of the PC (not shown) connected to the I / F 6 is read into the auxiliary storage device 5 or the data of the auxiliary storage device 5 is written in the PC. That is, when the data of the PC is read and stored in the auxiliary storage device 5, the data read via the I / F 6 is temporarily stored in the RAM 3, the data is transferred to the control circuit 4, and the write command of the CPU 1 is issued. Is written to the disk of the auxiliary storage device 5.

On the contrary, the necessary data from the auxiliary storage device 5 is required.
When reading the data and writing the data to the PC, the CPU 1 designates the address storing the required data to the control circuit 4 and gives a read command, so that the necessary data is read from the auxiliary storage device 5. Is stored in the RAM 3 via the control circuit 4, and the data stored in the RAM 3 is transferred to the I / F.
Writing to PC via 6.

On the other hand, the reset signal generation circuit 7 externally forcibly generates a reset signal 101 for resetting the entire PC including the auxiliary storage device 5, and when the switch 10 is in the open state, the input of the molding machine 8 is performed. Is at the H level via the resistor 9, the reset signal 1 output from the shaper 8
01 also becomes H level, and CPU 1 and control circuit 4
Are input to the respective reset terminals of, and as a result, the CPU 1 and the control circuit 4 are not activated, and the operation is executed according to the program of the ROM 2.

Next, when the push button switch 10 is pushed down to a closed state, the input of the molding machine 8 becomes L level,
Since the reset signal 101 output from the molding machine 8 also becomes L level, the CPU 1 and the control circuit 4 immediately enter the reset state.

FIG. 10 is a block diagram showing another concrete example of a conventional PC, and reference numerals 1 to 6 are exactly the same as those in FIG. 11 is a transformer for converting an AC voltage into a secondary voltage, for example, AC30V, and 12 is a DC constant voltage from the secondary voltage to be a power source for the PC, for example, DC5V10.
A constant voltage generating circuit for generating 2 is a voltage detecting circuit for detecting a DC voltage value and outputting a reset signal 103 when the value is lower than a certain constant value (DC 4.75V, for example). The reset signal 103 is CPU 1 and control circuit 4
Input to each reset terminal.

Therefore, according to this conventional example, the DC voltage 1
When 02 is in the normal range (for example, DC 4.75 to 5V), the reset signal 103 becomes H level, so the CPU
1 and the control circuit 4 are not reset and perform normal operation, and the DC voltage 102 is an abnormal voltage (for example, 4.75V DC).
(Below), the reset signal 103 becomes L level, and the CPU 1 and the control circuit 4 are in a reset state.

Therefore, only when the DC voltage 102 is in the normal range, the data is read from the PC and written in the auxiliary storage device 5, or conversely, another data is stored in the auxiliary storage device 15. Can be read and written to the PC. Of course, the reading and writing procedure at this time is stored in the ROM 2 in advance, and the read data is read.
RAM 3 is used to temporarily store the data.

[0010]

Since the conventional PC is constructed as described above, when the reset operation is forcibly performed on the control circuit 4 during the writing operation to the auxiliary storage device 5, Alternatively, if the power supply voltage drops for some reason and a reset signal is output from the voltage detection circuit, the data write operation will be interrupted,
As a result, there is a problem that the data is destroyed.

The present invention has been made to solve the above problems, and in the case where a reset signal is output during a data writing operation to an auxiliary storage device such as a floppy disk or a hard disk. Also, the object is to obtain a PC capable of preventing the destruction of data.

[0012]

The PC according to the present invention is
A programmable controller including at least a microprocessor, a program storage memory, an arithmetic operation memory, and a control circuit for controlling writing and reading operations with respect to an auxiliary storage device, the reset operation being performed for the microprocessor and the control circuit. A reset signal generating means for applying the reset signal and a delay circuit for delaying the reset signal for a predetermined time and inputting the delayed reset signal to the microprocessor and the control circuit are provided.

Further, an instantaneous power failure detection circuit for detecting an instantaneous power failure of the AC power supply and a voltage detection circuit for detecting a voltage drop of the DC power supply voltage are provided, and the output of the instantaneous power failure circuit is input to the CPU as an interrupt signal and the voltage is detected. The output of the circuit is input to the control circuit of the auxiliary storage device as a reset signal.

[0014]

According to the present invention, the reset signal output from the reset signal generating means is input to the CPU as an interrupt signal and is input to the auxiliary storage device control circuit with a delay of a predetermined time due to the action of the delay circuit, during this delay period. Then, the data write operation to the auxiliary storage device is continued.

By inputting the power failure detection signal of the instantaneous power failure detection circuit to the CPU as an interrupt signal, the CP
By suspending the operation of U and inputting the voltage drop signal of the voltage detection circuit to the auxiliary storage device control circuit as a reset signal longer than the processing time of the auxiliary storage device, the data writing operation to the auxiliary storage device can be performed. Let it continue.

[0016]

【Example】

Example 1. FIG. 1 is a block diagram showing an embodiment of the present invention. Reference numerals 1 to 10 are the same as those of the conventional device. Reference numeral 21 denotes a delay circuit to which the reset signal 101 which is the output signal of the reset signal generation circuit 7 is input. Are input respectively. Also, reset signal 1
01 is directly input to the CPU 1 at the same time. Note that FIG.
3 shows a concrete circuit example of the delay circuit 21,
In the figure, 22 is a molding machine, 23 is a capacitor, and 2
4 and 25 are resistors and 26 is a diode,
2 shows a delay circuit when the charge and discharge time constants are the same, and FIG.
Shows delay circuits when charging / discharging time constants are made different.

The operation of the embodiment shown in FIG. 1 will be described. C
The operations of the PU 1 and the auxiliary storage control circuit 4 are basically the same as the conventional ones, and therefore the reset operation, which is a feature of the present invention, will be described. That is, the push button switch 1 of the reset signal generating circuit 7 is operated while the auxiliary storage control circuit 4 is operating.
When 0 is closed, the reset signal 101, which is the output of the reset signal generation circuit 7, becomes active as in the conventional case. That is, in the embodiment shown in FIG. 1, the L level is set, and as a result, the CPU 1 interrupts the work in progress and executes a predetermined interrupt process, and does not give a new command to the auxiliary storage control circuit 4. At the same time, the reset signal 101 is also input to the delay circuit 21, so that the delay circuit itself also becomes active.

Here, as shown in FIG. 4, the delay circuit 21
Is set to output the delay reset signal 110 after a predetermined delay time t1 from the input, the push button switch 10 is closed when the closing time t3 of the push button switch 10 is longer than the delay time t1. If a write command is issued from the CPU 1 to the control circuit 4 immediately before the control circuit 4 is executed, the control circuit 4 writes data to the auxiliary storage device 5.
The data write operation is continuously executed.

Since the delay time t1 of the delay circuit 21 is set longer than the write operation duration time t2 by the control circuit 4, the delay circuit 2 is set after the write operation is completed.
A delayed reset signal is output from 1. The delayed reset signal 110 resets the CPU 1 and the control circuit 4 to bring the entire system into a reset state. That is, the control circuit 4
Is reset after the control operation is completed, the write data in the auxiliary storage device 5 is not destroyed.

Next, when the closing time of the push button switch 10 is shorter than the delay time t1, the CPU 1 simultaneously executes interrupt processing, but the switch 10 is opened before the delay reset signal 110 is output from the delay circuit 21. Because C
PU1 ends the interrupt processing, and resumes the work being executed before the switch 10 is closed. At this time, as a matter of course, since the delayed reset signal 110 does not become active, it is not reset as a system, and as a result, the problem that the data is destroyed does not occur.

In this embodiment, the reset signal generating circuit 7 has a circuit configuration for shaping a signal by turning on and off the push button switch 10, but it may have a circuit configuration by an ONE shoot circuit, for example. Although the guarantee of the write operation of the system including the control circuit 4 and the auxiliary storage device 5 has been described, the control circuit 4 and the auxiliary storage device 5 may be used as another system that operates asynchronously by a command from the CPU 1. May be configured.

Example 2. In FIG. 6, reference numerals 1 to 6 and 11 to 13 are the same as the conventional ones. Reference numeral 14 denotes an instantaneous power failure detection circuit connected to the output side of the transformer 11, which detects when an instantaneous power failure has occurred in the power source and detects an instantaneous power failure signal 12
0 changes from H level to L level. The instantaneous blackout signal 120 is input to the non-maskable interrupt terminal (hereinafter referred to as NMI terminal) of the CPU 1.

Next, the operation will be described. When the CPU 1 tries to write the data in the auxiliary storage device 5 through the control circuit 4 and an instantaneous blackout occurs at time t1 as shown in FIG. 7, the detection circuit 13 generates an instantaneous blackout signal 120. Here, the time t2 is a delay time until the instantaneous blackout signal 120 is generated, and is normally set to several milliseconds. Therefore, when the instantaneous blackout time t1 is shorter than the delay time t2, the instantaneous blackout signal remains at the H level and the power supply voltage 102 of the CPU 1 and the like is in the normal range, so that no problem occurs.

Next, when the instantaneous blackout time is around 10 milliseconds,
The instantaneous power failure signal 120 changes from H level to L level, and CP
U1 is the highest priority work being executed, that is, the auxiliary storage device 5
The data write operation to is interrupted and NMI processing is executed. In this NMI processing, the CPU 1 checks whether or not there is an instantaneous blackout. Therefore, when the power is restored, the instantaneous blackout signal 1 is output after the delay time t3 (usually 2 to 3 milliseconds).
02 becomes H level, the NMI process is terminated, and the write operation to the auxiliary storage device 5 is restarted. However, the time t4 until the power supply voltage decreases to 0 volt is normally maintained longer than the instantaneous blackout time, so the voltage detection circuit 13
Since the reset signal 103 output from is not active and the CPU 1 and the control circuit 4 are not reset,
There is no problem at this time.

Next, the case where the instantaneous blackout time t1 is longer than about 10 mm will be described. In this case, the instantaneous blackout signal 120
Is the same as the operation when the instantaneous blackout time t1 is about 10 and several milliseconds, and is different in that the reset signal 103 is output. That is, the time t5 when the instantaneous blackout occurs and the reset signal 103 becomes active.
However, if this occurs while writing data to the auxiliary storage device 5, data destruction occurs. However, in the present invention, the reset signal 103 becomes active after writing data to the auxiliary storage device 5. That is, CP
U1 receives N by the instantaneous blackout signal 120 based on the instantaneous blackout time t1.
Since the MI process is executed, a new command is not given to the control circuit 4 in the NMI process, and the reset active time t5 is set to be equal to or longer than the maximum processing time T (not shown) of the processing time for the command of the control circuit 4. If this is done, the reset signal 103 becomes active after the write operation of the control circuit 4 is completed, so that the write data to the auxiliary storage device 5 is not destroyed.

Since the maximum processing time T is uniquely determined by the type of the CPU 1, the software used, and the type of the control circuit 4, it is output from the constant voltage generating circuit 12. Needless to say, the following formula can be easily realized by increasing the holding time of the power supply voltage 102 and increasing the capacitance of the capacitor. Maximum processing time T <reset active time t5 (1) Further, when the instantaneous power failure is restored as shown in FIG. 7, the reset signal 103 remains even if the power supply voltage becomes the guaranteed voltage or lower (for example, 4V). Since it is active, there is no problem, and even if the power supply voltage gradually rises (for example, DC4V to 5V), the power supply voltage is normal voltage (for example, D
There is no problem in operation because the reset signal is active for a certain period of time after C4.75V). Here, the fixed time is indicated by the reset recovery time t6 in FIG.

Next, the case where the power is accidentally turned off during writing to the auxiliary storage device 5 will be described. Also in this case, the operation of the instantaneous blackout signal 120 is the same as that at the momentary power failure. However, although the reset signal 103 is surely activated every time regardless of the length of the instantaneous blackout, since the above formula (1) is satisfied, the data destruction of the auxiliary storage device 5 does not occur for the same reason.

Although the interrupt to the CPU 1 is input to the NMI terminal in this embodiment, it may be a normal maskable interrupt process or a high active interrupt process. Further, although the voltage detection circuit 13 is configured to detect the DC power supply voltage and output the reset signal, even if the time is set by the timer or the like based on the change of the instantaneous blackout signal and the above formula (1) is satisfied. Good. Also, reset signal 1
Although 03 is input only to the CPU 1 and the control circuit 4, the same effect can be obtained by inputting it to another block or another functional block not shown.

[0029]

Since the present invention is configured as described above, the auxiliary storage is executed even if a reset operation is executed while data is being taken into the auxiliary storage or an unexpected power failure occurs in the power supply. The device data can be prevented from being destroyed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a reset signal generating circuit of the present invention.

FIG. 3 is a diagram showing a reset signal generating circuit of the present invention.

FIG. 4 is a diagram showing an operation pattern according to the first embodiment of the present invention.

FIG. 5 is an operation flow diagram of the first embodiment of the present invention.

FIG. 6 is a block diagram showing a second embodiment of the present invention.

FIG. 7 is a diagram showing an operation pattern according to the second embodiment of the present invention.

FIG. 8 is an operation flow diagram of the second embodiment of the present invention.

FIG. 9 is a block diagram of a conventional programmable controller.

FIG. 10 is a block diagram of a conventional programmable controller.

[Explanation of symbols]

 1 Central Processing Unit (CPU) 2 ROM 3 RAM 4 Auxiliary Storage Device Control Circuit 5 Auxiliary Storage Device 6 PC Interface 7 Reset Signal Generation Circuit 8 Molding Machine 9 Resistor 10 Push Button Switch 11 Transformer 12 Constant Voltage Generation Circuit 13 Voltage Detection Circuit 14 Instantaneous power failure detection circuit 101 Reset signal 102 DC voltage 103 Reset signal 110 Delayed reset signal 120 Instantaneous power failure signal

Claims (2)

[Claims] 1. A programmable controller including at least a microprocessor, a program storage memory, an arithmetic operation memory, and a control circuit for controlling writing and reading operations with respect to an auxiliary storage device, wherein the microprocessor and the control circuit. And a delay circuit for delaying the reset signal for a predetermined time and inputting the reset signal to the microprocessor and the control circuit. 2. A programmable controller including at least a microprocessor, a program storage memory, a memory for arithmetic work, and a control circuit for controlling writing and reading operations with respect to an auxiliary storage device, the instantaneous power failure of an AC power supply. An instantaneous power failure detection circuit for detecting and a voltage drop detection circuit for detecting a voltage drop of the DC power supply voltage, wherein the output signal of the instantaneous power failure detection circuit is input to the microprocessor as an interrupt signal. Programmable controller.