JP2002091632A - Computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a computer system capable of preventing a trouble in recording of data while suppressing the complication and cost increase of the computer system. SOLUTION: Data for a prescribed size is stored in the writing preparation area of a RAM from stored data (S2) to make an inquiry about the presence and absence of the occurrence of power interruption (S3). In the absence of power interruption (S4), the data in the writing preparation area is written in a nonvolatile auxiliary storage device (S5). In this case, the data is written with the prescribed size as a unit and the prescribed size is set so that a time required for writing the data into the nonvolatile auxiliary storage device may have a value sufficiently smaller than a dropping time between the timing of reporting a power interruption detection signal and a time when DC power voltage is lowered than the lower limit of a rated voltage value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer device in which a main data storage unit writes data to a storage medium constituted by a nonvolatile auxiliary storage device.

[0002]

2. Description of the Related Art Conventionally, in a computer device or the like, particularly a unitized computer device used for embedding in a device, if a power-off operation is performed or a power failure occurs during a data update process, the data being recorded is deleted. A part or all of the data may be lost, or electrical or mechanical damage may be caused in the operation of the non-volatile auxiliary storage device in which data is stored.

In order to prevent troubles such as data loss or failure due to such a power supply, in a power-off operation, the power supply is instructed by a computer device so that the power supply is not actually turned off until the data updating process is completed. The power supply is performed via the uninterruptible power supply for the disconnection process and the power failure.

[0004]

However, in such a device, a power supply disconnecting device for cutting off the power after the data update is completed after maintaining the power supply until the data update is completed is required. At the same time, an uninterruptible power supply is required as a measure against power failure. This has led to complications and increased costs of the computer device.

The present invention has been made in view of such conventional problems, and provides a computer device capable of preventing a trouble at the time of data recording while suppressing the complexity and cost increase of the computer device. The purpose is to do so.

[0006]

In order to solve the above-mentioned problems, a computer device according to the present invention comprises control means for reading data from a main storage device and storing the data in a nonvolatile auxiliary storage device. In a computer device in which reading is performed in a unit of a predetermined capacity, a writing time to the nonvolatile auxiliary storage device is such that a supply voltage to the control unit after a power failure is detected is lower than a rated value that guarantees a normal operation. The predetermined volume was set so as to be within the descent time until the time.

That is, in the computer device, when a power failure occurs during the execution of the writing process and the power supply is cut off, the supply voltage supplied to the control means gradually drops without being cut off immediately. At this time, the control means performs reading of the data in units of a predetermined capacity, and the capacity is determined by the writing time to the nonvolatile auxiliary storage device and the supply voltage after the power failure is detected. It is set so that it is within the descent time until the value falls below the rated value.

[0008] Therefore, data writing to the nonvolatile auxiliary storage device can be completed during a period from when the power failure is detected to when normal operation of the control unit is disabled.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a computer device 1 according to the present embodiment. The computer device 1 is mainly configured with a CPU (Central Processing Unit) 2.

The CPU 2 has a ROM (Read Only Memory) 1 storing a program to be executed by the CPU 2.
1 is connected via a bus 13 to a RAM (Random Access Memory) 12 serving as a main storage device for storing data and the like being processed, and the bus 13 is used to exchange data with the outside. 1 interface 14 and CR
A T15 and a second interface 17 to which a keyboard 16 is connected are connected. In addition, the bus 13
Is connected to an auxiliary storage device 16. The auxiliary storage device 16 is constituted by a semiconductor disk device in which a main data storage section is constituted by a flash memory which is a semiconductor nonvolatile memory.

The computer apparatus 1 is provided with a power supply unit 21 for generating a DC power supply used in the computer apparatus 1 from a commercial power supply. The power supply unit 21 includes an AC / DC power supply device 22 for rectifying an alternating current into a direct current. Power from the AC / DC power supply 22 is supplied to each of the blocks 2, 11, 12, 16, 24 (RAS board described later)
Supplied to Further, the power supply unit 21 includes:
A power failure detection circuit 23 that monitors a power failure of the commercial power supply is provided. When the power failure detection circuit 23 detects the interruption of the commercial power supply, the RAS (Reliability Availiabilit
y Serviceability) It is configured to output a power failure detection signal to the board 24.

The RAS board 24 is connected to the CPU 2 and is configured to output an interrupt signal generated based on the power failure detection signal from the power supply unit 21 to an interrupt port of the CPU 2.

Thus, the CPU 2 having received the interrupt signal is configured to start the power failure handling process prior to the current process in the computer device 1. That is, the CPU 2 is configured to stop processing involving generation of new write data to the auxiliary storage device 16 and store only the data currently waiting for writing in the auxiliary storage device 16. I have.

FIG. 2 is a timing chart showing the process from the occurrence and detection of a power failure to the storage of data in the auxiliary storage device 16. In the section A in the figure, the power failure detection circuit 23 of the power supply unit 21 detects a commercial power failure. Upon detection, a power failure detection signal is notified to the RAS board 24 at timing B.

When the RAS board 24 receives the notification of the power failure detection signal, the RAS board 24 outputs an “L” output interrupt signal to the CPU 2.
And causes the CPU 2 to interrupt the current process in the computer device 1 and start the power failure handling process with priority. As a result, the data writing process to the auxiliary storage device 16 is completed by the time C when the DC power supply voltage supplied to each of the blocks 2, 11, 12, 16, and 24 in the computer device 1 falls below the lower limit of the rated voltage value. Is configured to end.

FIG. 3 shows an example of the data write time of the semiconductor disk device used as the auxiliary storage device 16. In the computer device 1 of the present embodiment, the write data size (capacity) to be written to the semiconductor disk device.
The relationship between the write time 31 and the required time 32 as the write time required for writing in the auxiliary storage device 16 is shown.

In the timing chart of FIG. 2 described above, when the time difference from the timing B at which the power failure detection signal is notified to the time C at which the DC power supply voltage falls below the lower limit of the rated voltage value is set as the descent time t, Needs to be set to a value smaller than the fall time t. At this time, considering that there is already data being written to the semiconductor disk device, t>
If it is set to be 2T, it can be sufficiently satisfied in practical use. Here, the case where the time difference from the timing B at which the power failure detection circuit 23 notifies the power failure detection signal to the time C at which the DC power supply voltage falls below the lower limit of the rated voltage value is set as the fall time t has been described as an example, The time difference between the time when the RAS board 24 outputs the interrupt signal to the CPU 2 and the time C when the voltage falls below the rated voltage value may be set as the descent time t.

That is, in the computer device 1 of the present embodiment, the safe range is a data capacity of 4096 bytes in which the value of the descent time t is about 100 ms and the time T required for one write is 32 ms. it is conceivable that. The descent time t is determined by the capacity of the power supply unit 21 in the smoothing circuit and the respective blocks 2, 11, 12,
This is a value that varies from system to system depending on the power consumption at 16 and 24. The required time 32 is set in the auxiliary storage device 1.
6 and the performance of CPU 2 and RAM 1
This value varies from system to system according to an operation clock such as 2.

In this embodiment having the above-described configuration, the procedure for dividing large-capacity data prepared in the RAM 12 for each predetermined write size and storing the divided data in the semiconductor disk device of the auxiliary storage device 16 is as follows. This will be described according to the flowchart shown in FIG.

First, after a large amount of data to be stored in the semiconductor disk device is prepared in the RAM 12 (step S
1: hereinafter step notation), obtain data of a predetermined size (4096 bytes in the case of the computer device 1 in the present embodiment) from the beginning of the remaining write data, and write the data allocated to the RAM 12 It is stored in the preparation area (S2).

Then, the state of the interrupt port connected to the RAS board 24 is confirmed, and the RAS board 24 is inquired about the occurrence of a power failure (S3), and it is determined whether or not a power failure has occurred (S4). At this time, if a power failure has not occurred, the data stored in the write preparation area of the RAM 12 is written to the semiconductor disk device in the auxiliary storage device 16 (S5).

At this time, if a power failure occurs during the writing process to the semiconductor disk device and the supply of commercial power to the power supply unit 21 as a power supply unit is interrupted, the power supply unit 21 Each block 2, 1
The DC power supply voltage supplied to the blocks 1, 2, 16, and 24 is not immediately cut off, but gradually drops, and
It falls below the normal shutdown voltage value of the system consisting of 11, 12, 16 and 24 and finally reaches zero. At this time, the CPU 2 reads the data in units of a predetermined size (4096 bytes), and the predetermined size is such that the time T (32 mS) required for writing data to the semiconductor disk device is as shown in FIG. The falling time t (100 m) from the timing B when the power failure detection signal is notified to the time C when the DC power supply voltage falls below the lower limit of the rated voltage value
The value is set to a value sufficiently smaller than S).

Therefore, from the timing B at which the power failure detection signal is notified, the blocks 2, 11, 12, 16, 2
4, that is, the period until the normal operation of the system becomes impossible, the data writing to the semiconductor disk device can be completed.

Therefore, in the computer device 1, especially in the unitized computer device 1 used for assembling the device, there is no need for a mechanism for electronically turning off the power supply, and without using an uninterruptible power supply device. Troubles such as loss of data and failure of equipment with the semiconductor disk device can be prevented.

Next, it is determined whether or not the remaining write data remains (S6). If the write data does not remain, the process is terminated. If the write data remains, the process branches to the step S2 to repeat the steps S2 and S3 until the data writing to the semiconductor disk device is completed. Steps S5 to S5 are executed.

On the other hand, in step S4, if "L" input to the interrupt port is detected and occurrence of a power failure is confirmed, the flow branches to step S3 to execute R
The inquiry to the AS board 24 and the confirmation of the occurrence of the power failure are repeatedly executed (S4).

Thus, when a power failure occurs, the execution of the next writing process (S5) can be stopped after the writing of the data of the predetermined size (4096 bytes) is completed. Thus, interruption of the writing process due to a power failure during writing to the semiconductor disk device can be prevented.

When the "L" input to the interrupt port is a disturbance factor such as noise, the input to the interrupt port becomes "H". As a result, in step S4, it can be determined that the power failure was erroneously detected, and the writing of the data stored in the write preparation area of the RAM 12 to the semiconductor disk device is restarted (S5). Until the writing is completed, the execution of each of the steps S2 to S5 can be continued.

[0029]

As described above, in the computer apparatus according to the present invention, data is written to the semiconductor nonvolatile memory during a period from the time when the power failure is detected until the normal operation of the control means becomes impossible. Can be completed.
For this reason, when a power failure is detected, the execution of the next writing process is stopped when the data writing is completed, so that the writing caused by the power failure during the writing to the semiconductor nonvolatile memory is stopped. Interruption of processing can be prevented.

This makes it possible to prevent a problem that part or all of the data being written is lost. Also, due to the voltage drop generated during writing,
In the operation of the semiconductor nonvolatile memory, malfunctions such as functional damage can be prevented without providing a disconnection process at the time of power-off or taking power-off measures such as installing an uninterruptible power supply.

Therefore, it is possible to reliably prevent a trouble at the time of data recording while suppressing the complexity and cost increase of the computer device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram illustrating a process from the occurrence of a power failure to a drop in DC power supply voltage according to the embodiment.

FIG. 3 is a diagram showing an example of a relationship between a write data size to be written to the semiconductor disk device of the embodiment and a time required for writing in an auxiliary storage device.

FIG. 4 is a flowchart showing an operation of the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Computer apparatus 2 CPU 12 RAM 16 Auxiliary storage device 21 Power supply unit 23 Power failure detection circuit T Required time t Fall time

Claims (1)

[Claims] 1. A computer device, comprising: control means for reading data from a main storage device and storing the data in a nonvolatile auxiliary storage device, wherein the reading of the data is performed in units of a predetermined capacity. The predetermined capacity is set so that the writing time of the power supply is within a fall time from the detection of the power failure to the time when the supply voltage to the control means falls below the rated value that guarantees normal operation. Computer device.