JP2001282402A - Recording medium controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a recording medium controller capable of preventing a damage of a recording medium in the case of plug and play or generation of an abnormality. SOLUTION: A reading operation or a writing operation of data to the recording medium 1a is controlled by a recording medium control circuit 2 and the abnormality of a primary power source 4 is detected by a primary power source monitoring circuit 3. The recording medium 1a is controlled to continue an operation until an operation for one sector is completed and not to be transited to a new operation after a series of operations are completed when the abnormality is detected especially in the recording medium control circuit 2. Thus, the damage of the recording medium such as damage of a sector is prevented since interruption of an operation in timing when the damage of the recording medium 1a is the most incidental is evaded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a recording medium control device applied to communication equipment and the like.

[0002]

2. Description of the Related Art FIG. 18 is a schematic diagram showing a backup system at the time of hot swapping described in Japanese Patent No. 2885136 "Monitoring and Control System". In this method, the CPU (Cent
ral Processing Unit (central processing unit) The data at the time of insertion / extraction is written to the backup memory 114 by the protect switch 103 which is linked when the substrate 101 is inserted / extracted, and the local path 113 to the backup memory 114 is closed.

[0003]

When a flash memory card is used as such a data backup memory, one sector is the minimum data unit.
One sector is composed of 512 bytes and performs error detection and correction processing in units of 512 bytes.

If the writing of 512 bytes is completed halfway, data inconsistency occurs in that sector, and the sector itself is determined to be invalid. If data writing is terminated as in the prior art at the time of insertion / removal of the board, the operation may be terminated in the middle of writing the sector.

[0005] As described above, even if the writing is completed in the middle of a sector and the next attempt is made to read the sector, since the writing in sector units has not been completed, the sector is determined to be invalid and the sector is used again. I can't do things.
Thus, there is a problem that the sector is destroyed each time the board is inserted and removed, and the capacity of the flash memory card is reduced each time.

In a flash memory card, data is read out in units of sectors in the same way as when data is written, so if one sector is read out halfway, the sector may be destroyed. This is because at the time of reading, data rewriting such as sector replacement is performed as internal processing of the flash memory card.

The above example relates to the insertion and removal of the board. However, there is also a problem of sector destruction when a power supply abnormality or a CPU abnormality occurs.

It is an object of the present invention to provide a recording medium control device which can prevent the recording medium from being destroyed when an abnormality occurs.

[0009]

According to the present invention, when an abnormality detection circuit detects an abnormality, the recording medium control circuit causes the recording medium to continue operating until the operation for the minimum data unit is completed. The recording medium control device is characterized in that after a series of operations is completed, control is performed so as not to shift to a new operation.

The abnormality detection circuit according to the present invention is constituted by a power supply monitoring circuit for monitoring electric power supplied from the outside.

The abnormality detection circuit according to the present invention comprises a secondary power supply monitoring circuit for monitoring power supplied from the secondary power supply.

Further, the abnormality detecting circuit of the present invention comprises a reset monitoring circuit for monitoring a reset switch.

Further, the abnormality detecting circuit according to the present invention comprises a CPU monitoring circuit for monitoring the CPU.

Further, the abnormality detecting circuit according to the present invention comprises a vibration monitoring circuit for monitoring vibration.

Further, the recording medium control circuit of the present invention collectively performs reading or writing of the minimum data unit on the recording medium using the data transmission / reception memory.

The minimum data unit according to the present invention is constituted by one file of one sector or a plurality of sectors of the recording medium.

Further, the present invention further includes a communication circuit for transmitting data written to the recording medium in the active system and receiving data to be written in the recording medium in the standby system.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a block diagram showing an electric configuration of a hot-swap circuit board as a first embodiment. The hot-swap circuit board includes a recording medium control circuit 2, a primary power supply monitoring circuit 3, a CPU 5, a transmission / reception memory 10, a secondary power supply 14, and a secondary power supply monitoring circuit 15 on a substrate 20.
Which is a printed circuit board which can be inserted into and removed from a communication device main body such as a subscriber transmission device in a live state. However, the present invention is not limited to a communication device, and can be applied to a computer device using a recording medium.

The recording device 1 is a storage device, such as a flash memory card, which is detachable from the substrate 20, and includes a drive (read / write device) and a medium (recording medium).
And are integrated. Used for data backup. In this embodiment, a flash memory card will be described as an example. However, the recording device 1 is not limited to this, and may be integrated with a medium such as a hard disk drive, or may be a CD-R (Compact Disk-Recordable).
e) It may be separate from the media like a drive. Also,
The recording method may be a magnetic recording method, an optical recording method or a magneto-optical recording method.

The recording medium control circuit 2 controls a data read operation or a data write operation on the recording medium 1a. The CPU 5 controls the recording medium control circuit 2 according to a predetermined program. The primary power supply monitoring circuit 3 monitors the voltage of the primary power supply 4 by constantly detecting the voltage, and detects an abnormality based on the fluctuation of the voltage. The secondary power supply monitoring circuit 15 monitors the voltage of the primary power supply 4 by constantly detecting the voltage, and detects an abnormality based on the fluctuation of the voltage.
The primary power supply 4 is a power supply provided in the main body, and supplies a high voltage of, for example, 48 volts into the substrate in a state where the substrate is inserted into the main body. The secondary power supply 14 drops the high voltage from the primary power supply 4 and supplies a low voltage of, for example, 3 volts and 5 volts to each circuit in the board. The transmission / reception memory 10 is a storage device for storing data for one sector of the recording medium 1a, and is a random access memory (RAM).
mory).

FIG. 2 is a timing chart showing an operation of writing one sector to the recording medium 1a. Signal WE
(Write Enable) * is a signal for instructing the recording medium 1a to write, and is transmitted from the recording medium control circuit 2 to the recording device 1 together with the write data. The signal BUSY * is
This signal indicates that access to the recording medium 1a is permitted or prohibited, and is transmitted from the recording device 1 to the recording medium control circuit 2. When the signal BUSY * is at the L level,
The recording device 1 itself is in operation, during which access such as writing is prohibited. Signal INT (INTerrupt) *
Is a signal for notifying the CPU 5 when the signal BUSY * is completed. The signal is transmitted from the recording medium control circuit 2 to the CPU 5 and used as an interrupt signal of the CPU 5. The L level of the signal INT * indicates that the signal BUSY * has ended.

FIG. 3 is a flowchart showing a procedure for writing one sector on the recording medium 1a. When a write operation is started in step a1, an instruction to write data of one sector (= 512 bytes) to the recording medium 1a is transmitted in the next step a2. When the transmission of the write command is completed, in the next step a3, the operation shifts to the write operation of the recording device 1, and an L level period of the signal BUSY * is generated. When the L-level period of the signal BUSY * ends, in the next step a4, an L-level period of the signal INT * is generated. In the next step a5, the CP
U5 releases the L level of INT *, and ends the write operation in step a6.

FIG. 4 is a flowchart showing an operation when a primary power supply abnormality is detected during writing of one sector to the recording medium 1a. First, in step b1, when the primary power supply monitoring circuit 3 detects a primary power supply abnormality, the process proceeds to the next step b2. The primary power supply abnormality is detected not only when the primary power supply 4 fails but also when the board 20 is removed from the main body, and the power supply is stopped. At step b2, the writing operation is monitored until the writing operation for the sector unit of the recording medium is completed. When the writing operation is completed, the process proceeds to the next step b3. In step b3, even when a new write command is issued from the CPU 5, the recording medium control circuit 2 refuses to shift to a new write cycle.

As a method of rejecting writing, the CP shown in FIG.
In response to an instruction from the CPU 5 on the U bus, the recording medium control device 2 keeps returning a retry signal. As a result, the same operation is possible from the viewpoint of the CPU 5 irrespective of whether or not a primary power supply abnormality has occurred.

At step b4, it is determined whether or not the abnormality of the primary power supply is continuously detected, and the processing of steps b3 and b4 is repeated until the abnormality is no longer detected. If no abnormality is detected, the process returns to the normal sequence in step b5. Here, it is possible to shift to a new write cycle.

As described above, by monitoring the primary power supply 4 and controlling the writing to the recording medium 1a, the primary power supply 4 during operation is controlled.
After the writing for the sector is completed, the operation is stopped, so that sector destruction of the recording medium 1a can be prevented.

FIG. 5 is a flowchart showing a write operation using the one-sector transmission / reception memory. Step c
When a write operation is started in 1, write data is written in the transmission / reception memory 10. In the next step c2, it is determined whether or not the writing of data for one sector into the transmission / reception memory 10 has been completed. After the data for one sector has been written, in the next step c3, the data in the transmission / reception memory 10 is collectively stored in the recording medium 1.
Write to a.

As described above, the one-sector transmission / reception memory 10
, It is possible to write data for one sector to the recording medium 1a at high speed. Further, even when the CPU 5 is interrupted, the writing speed to the recording medium 1a is not affected. further,
The one-sector transmission / reception memory 10 may be used at the time of reading data, and reading can be speeded up. By repeating the operation of FIG. 5 a plurality of times, all data can be written to the recording medium 1a.

In FIG. 1 to FIG. 5, the operation unit is one minimum data unit, but the data unit for managing the recording medium 1a is not necessarily one sector. As described above, in some cases, it is preferable that the operation unit is data for a plurality of sectors. in this case,
Unless the data is read out in units of one file, the data becomes meaningless and the software for processing the data may malfunction. In such a case, it is appropriate that the operation unit is one file. Hereinafter, an operation example when the operation unit is one file will be described.

FIG. 6 is a flowchart showing an operation when a primary power supply abnormality is detected during writing of one file unit to a recording medium. The flowchart of FIG.
The operation unit of the flowchart of FIG. 7 is changed for each file. That is, when the primary power supply monitoring circuit 3 detects a primary power supply abnormality in step d1, the process proceeds to the next step d2. In step d2, the writing operation is monitored until the writing operation for one file on the recording medium is completed, and when the writing operation is completed, the next step d
Proceed to 3. In step d3, even when a new write command is issued from the CPU 5, the recording medium control circuit 2 refuses to shift to a new write cycle. Step d
In step 4, it is determined whether or not the abnormality of the primary power supply is continuously detected.
3 and step d4 are repeated. If no abnormality is detected, the process returns to the normal sequence in step d5. Here, a new write cycle can be executed.

As described above, by monitoring the primary power supply 4 and controlling the writing to the recording medium 1a, at least the writing operation for one file in operation is completed, so that sector destruction of the recording medium 1a can be prevented. . Also,
Similarly, by controlling the operation of reading data for each file, sector destruction of the recording medium 1a can be prevented.

FIG. 7 is a timing chart showing an operation of reading one sector from the recording medium 1a. Signal OE
(Output Enable) * is a signal for instructing data reading for one sector from the recording medium 1a, and is transmitted from the recording medium control circuit 2 to the recording apparatus 1. The read data is transmitted from the recording apparatus 1 to the recording medium control circuit 2 substantially at the same time as the generation period of the signal OE *. Signal BUSY *
The signal INT * is the same signal as in FIG.

FIG. 8 is a flowchart showing an operation when a primary power supply abnormality is detected during reading of one sector from the recording medium 1a. The operation of each step is obtained by replacing the write operation in the flowchart of FIG. 4 with a read operation. That is, when the primary power supply monitoring circuit 3 detects a primary power supply abnormality in step e1, the process proceeds to the next step e2. In step e2, the read operation is monitored until the operation for the sector unit is completed. When the operation is completed, the process proceeds to the next step e3. In step e3,
Even when a new read command is issued from the CPU 5, the recording medium control circuit 2 refuses to shift to a new read cycle. In the next step e4, it is determined whether or not the abnormality of the primary power supply is continuously detected, and the processing of steps e3 and e4 is repeated until the abnormality is no longer detected. If no abnormality is detected, the process returns to the normal sequence in step e5. Even in the read operation, if a primary power supply abnormality is detected, a new read cycle does not start.

As described above, by monitoring the primary power supply 4 and performing read control on the recording medium 1a, the primary power supply 4 during operation is controlled.
Since the read operation on the sector is stopped after the operation is completed, the sector destruction of the recording medium 1a can be prevented.

FIG. 9 is a timing chart showing a command issuing operation to the recording apparatus 1. Signal WE * ・ BUS
Y * INT * is the same signal as in FIG. The command is a command other than the read command and the write command, for example, for specifying an access area of the recording medium 1a. When the L level of the signal BUSY * ends, a command can be issued after the signal INT * is generated.

FIG. 10 is a flowchart showing an operation when a primary power supply abnormality is detected while a command is issued to the recording apparatus 1. When the primary power supply monitoring circuit 3 detects a primary power supply abnormality in step f1, the process proceeds to the next step f2. In step f2, the signal BUSY * is monitored, and when the L level of the signal BUSY * ends, the process proceeds to the next step f3. In step f3, the issuance of a new command is prohibited, and in the next step f4, it is determined whether the abnormality of the primary power supply is continuously detected. Steps f3 and f4 until no abnormality is detected.
Is repeated, and when no abnormality is detected, the process returns to the normal sequence in step f5. in this way,
If a primary power supply abnormality is detected at the time of issuing a command, no new command is issued.

As described above, the issuance of the new command is suspended until the primary power supply 4 operates normally, so that the operation can be promptly resumed when the primary power supply 4 recovers.

Although the operation at the time of abnormality in the primary power supply has been described above, the same applies to the operation at the time of abnormality of the secondary power supply 14 in FIG. That is, the secondary power supply monitoring circuit 1
5, the secondary power supply 14 is monitored, and writing / reading control to / from the recording medium 1a is performed according to the procedures shown in FIGS. 4 and 8, thereby preventing sector destruction of the recording medium 1a. Further, by monitoring the secondary power supply 14 and controlling the command issuance according to the procedure shown in FIG. 10, the operation can be promptly resumed when the secondary power supply 14 recovers.

(Second Embodiment) FIG. 11 is a block diagram showing an electrical configuration of a hot-swap circuit board as a second embodiment of the present invention. Recording device 1, recording medium control circuit 2,
The CPU 5 and the one-sector transmission / reception memory 10 are the same as those in FIG. The reset switch 7 may be a hardware switch that can be operated by a user or a software switch that can be switched by internal processing. The reset monitoring circuit 6 monitors the reset switch and detects a reset of the device. ROM (Read Onl
y Memory) 13 stores a program used by the CPU 5, and the program is stored in a RAM (Random Acc.).
ess Memory) 12. The CPU 5 controls the recording medium control circuit 2 according to the loaded program. The RAM 12 also temporarily stores intermediate calculation results of the CPU 5 and the like.

FIG. 12 is a flowchart showing the operation when the device reset is detected during the writing of one sector to the recording medium 1a. If the reset monitoring circuit 6 detects a device reset in step g1, it is determined in step g2 whether or not writing of one sector to the recording medium 1a has been completed. Until the writing operation of one sector is completed, the writing operation to the recording medium 1a is monitored in step g2, and when the writing of one sector is completed, the process proceeds to the next step g3. In step g3,
No new write cycle is generated, that is, writing to the next sector is prohibited. Finally, in step g4, the apparatus is reset, that is, the stored contents of the RAM 12 are erased and the program of the ROM 13 is reloaded.

As described above, when the reset monitoring circuit 6 detects a device reset, the operation is continued until data for one sector being written is written, and thereafter control is performed so as not to shift to a new write operation. Thus, it is possible to prevent the sector of the recording medium 1a from being destroyed due to the device reset. Further, by monitoring the device reset and controlling the read operation of the recording medium 1a, the recording medium 1a
Sector destruction can be prevented.

(Third Embodiment) FIG. 13 is a block diagram showing an electrical configuration of a hot-swap circuit board according to a third embodiment of the present invention. Recording device 1, recording medium control circuit 2,
The CPU 5 and the one-sector transmission / reception memory 10 are the same as those in FIG. The CPU 5 periodically reports information indicating that its own operation is normal to the CPU monitoring circuit 8. The CPU monitoring circuit 8 monitors the operation of the CPU 5 by detecting the report signal from the CPU 5. When the report signal cannot be detected normally, the CPU 5 determines that some abnormality has occurred.

FIG. 14 is a flowchart showing an operation when a CPU error is detected during the writing of one sector to the recording medium 1a. When the CPU monitoring circuit 8 detects an abnormality in the CPU 5 in step h1, it determines in step h2 whether data writing in sector units has been completed. If not, step h3
The recording medium control circuit 2 writes arbitrary data in the remaining area of the sector being written. When the operation to the sector being written is completed, the writing operation to the next sector is prohibited in step h4, and no new write cycle is generated. Finally, in step h5, all the device operations are stopped.

As described above, the CPU monitoring circuit 8
Is detected, data writing is continued until writing to the sector being written is completed, and then control is performed so as not to shift to a new writing operation, thereby preventing sector destruction of the recording medium 1a. Further, when an abnormality of the CPU 5 is detected, appropriate data is written to the recording medium 1a instead of the write data to be received from the CPU 5, so that even when the write data from the CPU 5 is interrupted, the sector destruction of the recording medium 1a is prevented. Can be prevented.
Further, by performing data read control of the recording medium 1a in a similar procedure, even when a CPU abnormality is detected during reading, the recording medium 1a can be prevented from being destroyed.

(Fourth Embodiment) FIG. 15 is a block diagram showing an electrical configuration of a hot-swap circuit board as a fourth embodiment of the present invention. Recording device 1, recording medium control circuit 2,
The CPU 5 is the same as in FIG. Vibration monitoring circuit 9
Is a circuit for detecting the vibration of the substrate, and is constituted by an acceleration sensor or the like. Although not shown in FIG. 15, using the same one-sector transmission / reception memory 10 of FIG.
Data reading / writing of the recording medium 1a may be performed.

FIG. 16 is a flowchart showing the operation when the substrate vibration is detected during the writing of one sector to the recording medium 1a. When the substrate vibration is detected in step i1, the process proceeds to step i2. The board vibration is detected when the board is removed from the main body in addition to when an earthquake occurs. In step i2, it is determined whether or not writing in sector units has been completed. The operation is continued until the writing to the writing sector is completed.
Proceed to 3. In step i3, no new write cycle is generated, that is, a write operation to the next sector is prohibited. Next, in step i4, it is determined whether or not the detection of vibration is continuing. Writing is prohibited while vibration is ongoing, and when vibration is no longer detected,
In the last step i5, the sequence is returned to the normal sequence. That is, a transition to a new write cycle is permitted.

As described above, when the vibration is detected, the data writing is continued until the writing to the sector being written is completed, and then the control not to shift to a new writing operation is performed. Can be prevented. In addition, by performing data read control of the recording medium 1a in a similar procedure, even when vibration is detected during reading, the recording medium 1a can be prevented from being destroyed. further,
When a vibration is detected during the command issuance, by performing control to prohibit the issuance of a new command until the vibration is no longer detected, the operation can be promptly resumed after the vibration has ceased.

(Fifth Embodiment) FIG. 17 is a block diagram showing a double system of a hot-swap circuit board as a fifth embodiment of the present invention. Recording device 1, recording medium control circuit 2, CP
U5 is the same as in FIG. The active and standby communication circuits 11 are circuits that perform data communication with each other. When receiving the abnormality detection signal from the primary power supply monitoring circuit 2, the working spare recognition circuit 16 recognizes that the own system is the working system or the spare system. Although not shown in FIG.
Data may be read / written from / to the recording medium 1a using the same memory as the one-sector transmission / reception memory 10 of FIG.

Next, the operation of the dual system when an abnormality of the primary power supply 4 is detected during the data write operation will be described.

During the operation of writing data to the active recording medium 1a, the primary power supply monitoring circuit 3 of the active system is used.
Detects the abnormality of the primary power supply 4, performs the same write control as in the first embodiment. At the same time, the primary power supply monitoring circuit 3 outputs the abnormality detection signal to the standby active recognition circuit 1 of the standby system.
Send to 6. Upon receiving this, the working preliminary recognition circuit 16
It is determined whether the own system is an active system or a standby system. If the current system is recognized, the abnormality detection signal is ignored, and if the current system is recognized, the abnormality detection signal is transmitted to the recording medium control circuit 2. Here, since it is a standby system, the abnormality detection signal is transmitted to the recording medium control circuit 2.

The standby recording medium control circuit 2 transmits the write data transmitted in this order to the active CPU 5, communication bus, communication circuit 11, intersystem bus, standby communication circuit 11, communication bus, and CPU 5. Receive. This write data is data that should be originally written on the active recording medium 1a, but is instead written on the standby recording medium 1a.

As described above, the active communication circuit transmits the data written in the recording medium in the active system, and the standby communication circuit receives the data and similarly writes the data in the standby recording medium. Even when switching between the system and the standby system,
The writing operation before the switching can be smoothly taken over.

[0053]

As described above, according to the present invention, when an abnormality is detected during a data read or write operation, the operation is continued at least for the minimum data unit during the read or write operation, and After the operation is completed, control is performed so as not to shift to the operation of the next minimum data unit, so that operation interruption at the timing when destruction of the recording medium is most likely to occur can be avoided, and destruction of the recording medium such as sector destruction can be prevented. Can be prevented.

According to the present invention, since the above-described operation control is performed when a power supply abnormality is detected, inappropriate interruption of operation due to insufficient power can be prevented, and destruction of the recording medium can be prevented.

Further, according to the present invention, since the above-described operation control is performed by detecting the abnormality of the secondary power supply, even if there is no abnormality in the primary power supply, destruction of the recording medium due to the abnormality of the secondary power supply. Can be prevented.

Further, according to the present invention, since the above-described operation control is performed by monitoring the on / off operation of the reset switch, the destruction of the recording medium due to the reset can be prevented.

According to the present invention, since the above-described operation control is performed by monitoring the CPU, it is possible to prevent the recording medium from being destroyed due to a failure of the CPU, for example, a thermal runaway.

Further, according to the present invention, since the above-described operation control is performed by monitoring the vibration, it is possible to prevent the recording medium from being destroyed due to the vibration. For example, if the substrate vibrates due to an earthquake, cracks may occur in the substrate, and the circuit on the substrate may be damaged, interrupting the operation on the recording medium. The interruption can prevent the recording medium from being destroyed.

According to the present invention, reading or writing to the recording medium is performed collectively by using a data transmission / reception memory having a data capacity of a minimum data unit for the recording medium. Interruption is less likely to occur, and the destruction of the recording medium can be more reliably prevented.

According to the present invention, the destruction of the recording medium can be reliably prevented by setting the minimum data unit to one sector.
Alternatively, by setting the minimum data unit to one file,
It is possible to avoid useless data read operation or write operation except valid data.

According to the present invention, the working communication circuit also transmits the data written to the recording medium in the working system to the spare system, and the data is received by the spare communication circuit and is also transmitted to the spare recording medium. Similarly, even when the active system and the standby system are mutually switched, the write operation from before the switching can be smoothly taken over.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart at the time of writing according to the first embodiment;

FIG. 3 is a flowchart showing a one-sector write procedure according to the first embodiment;

FIG. 4 is a diagram showing a state where 1 is written during writing of one sector in the first embodiment.
Flowchart showing operation when secondary power supply abnormality is detected

FIG. 5 is a flowchart showing a write operation using a one-sector transmission / reception memory;

FIG. 6 is a flowchart illustrating an operation when a primary power supply abnormality is detected during writing in file units according to the first embodiment;

FIG. 7 is a timing chart at the time of reading according to the first embodiment;

FIG. 8 is a flowchart illustrating an operation when a primary power supply abnormality is detected during reading of one sector according to the first embodiment;

FIG. 9 is a timing chart at the time of issuing a command according to the first embodiment;

FIG. 10 is a flowchart illustrating an operation when a primary power supply abnormality is detected at the time of issuing a command according to the first embodiment;

FIG. 11 is a block diagram showing an electrical configuration of a second embodiment of the present invention.

FIG. 12 is a flowchart illustrating an operation when a device reset is detected during the writing of one sector according to the second embodiment;

FIG. 13 is a block diagram showing an electrical configuration of a third embodiment of the present invention.

FIG. 14 is a flowchart illustrating an operation when a CPU abnormality is detected during the writing of one sector according to the third embodiment;

FIG. 15 is a block diagram showing an electrical configuration of a fourth embodiment of the present invention.

FIG. 16 is a flowchart showing the operation of the fourth embodiment when device vibration is detected during the writing of one sector.

FIG. 17 is a block diagram showing an electrical configuration according to a fifth embodiment of the present invention.

FIG. 18 is a schematic diagram showing a conventional backup method at the time of hot-swap.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Recording device 1a Recording medium 2 Recording medium control circuit 3 Primary power supply monitoring circuit 4 Primary power supply 5 CPU 6 Reset monitoring circuit 7 Reset switch 8 CPU monitoring circuit 9 Vibration monitoring circuit 10 1 Sector transmission / reception memory 11 Communication circuit 12 RAM 13 ROM 14 Secondary power supply 15 Secondary power supply monitoring circuit 20 Substrate

Claims (9)

[Claims] 1. A recording medium control device comprising: a recording medium control circuit for controlling a data read operation or a write operation on a recording medium; and a failure detection circuit for electrically detecting a failure. If an error is detected, the recording medium control circuit continues the operation until the operation for the minimum data unit on the recording medium is completed, and after the series of operations is completed, a control that does not shift to a new operation is performed. A recording medium control device characterized by performing: 2. The recording medium control device according to claim 1, wherein the abnormality detection circuit includes a power supply monitoring circuit that monitors power supplied from the outside. 3. An apparatus for lowering power supplied from the outside.
2. The recording medium control device according to claim 1, further comprising a secondary power supply, wherein the abnormality detection circuit is configured by a secondary power supply monitoring circuit that monitors power supplied from the secondary power supply. 4. A ROM for storing a program relating to a read operation or a write operation of the recording medium, and a CP for controlling a recording medium control circuit according to the program.
U, load program stored in ROM and CPU
And a reset switch for erasing data stored in the RAM and reloading a program in the ROM, wherein the abnormality detection circuit includes a reset monitoring circuit that monitors the reset switch. 2. The recording medium control device according to claim 1, wherein 5. The apparatus according to claim 1, further comprising a CPU for controlling a recording medium control circuit according to a predetermined program, wherein the abnormality detection circuit is configured by a CPU monitoring circuit for monitoring the CPU. Recording medium control device. 6. The apparatus according to claim 1, wherein the abnormality detection circuit includes a vibration monitoring circuit that monitors vibration.
The recording medium control device according to any one of the preceding claims. 7. A data transmission / reception memory for storing data of a minimum data unit in the recording medium, wherein the recording medium control circuit uses the data transmission / reception memory to store the minimum data unit in the recording medium. The recording medium control device according to any one of claims 1 to 6, wherein reading or writing is performed collectively. 8. The recording medium control device according to claim 1, wherein the minimum data unit is constituted by one file of one sector or a plurality of sectors of the recording medium. 9. A recording medium control device constituting one of a dual system comprising an active system and a standby system, wherein the active system transmits data written to the recording medium, and the standby system transmits data to the recording medium. 9. The recording medium control device according to claim 1, further comprising a communication circuit for receiving data to be written.