JPH0581922B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention applies to both peripheral devices and basic units.
The present invention relates to a method for resetting a sequence control device having a CPU, and particularly to a sequence control device that allows a programmer to be attached and detached during power supply.

[Prior art]

Both peripheral devices and basic unit have CPUs,
As a reset circuit for a sequence control device to which control power is supplied only from the basic unit, the circuit shown in FIG. 1 has been devised. The system shown in Figure 1 is the basic unit 1.
The reset terminals of CPU 3 of the peripheral device 2 and CPU 4 of the peripheral device 2 are commonly connected, and when the power is turned on with the peripheral device and the basic unit connected, both
The CPU is initialized and operates normally. However, if you separate the peripheral device 2 and attach it while power is being supplied to the basic unit 1, the reset signal has already been established as shown in the voltage waveform in Figure 2, so the CPU 4 of the peripheral device will not be initialized.
There was a drawback that the peripheral device 2 malfunctioned and could not be attached or detached while power was being supplied.

On the other hand, in the process of arriving at the present invention, the configuration shown in FIG. 3 was studied. This configuration consists of a basic unit 1 and peripheral devices 2.
Since both have reset circuits 5 and 6,
Even if a peripheral device is attached while power is being supplied to the basic unit 1, the CPU 4 is initialized after a predetermined delay time due to the resistor 10 and capacitor 12 of the reset circuit 6, so there is no malfunction due to attachment or detachment.

Here, the general operation of the reset circuit 5 of the basic unit will be explained with reference to FIGS. 3 and 4. This circuit is a circuit that detects momentary interruption of the AC power supply 7.
When the voltage is interrupted for one cycle or more, the comparator 8 is activated and the capacitor 9 is discharged through the resistor 14. The resistor 14 is set so that the capacitor 9 is quickly discharged. By discharging the capacitor 9, the CPU 3 of the basic unit is reset.

After the AC power supply 7 is restored, the resistor 15 and capacitor 9
After a predetermined delay time, the CPU 3 restarts. However, the control voltage Vcc is configured to be a specified voltage so that the comparator 8 and the like operate normally after one cycle of AC power interruption.

AC power supply 7 when peripheral equipment and basic unit are connected
When the main unit CPU 3 is momentarily interrupted, the basic unit CPU 3 is quickly reset by the above operation, but in the peripheral equipment, the capacitor 12 of the reset circuit 6 discharges through the diode 13, but since the voltage drop of the control power supply Vcc is slow, it takes time for the discharge to occur. It takes. When the AC power supply 7 is restored without sufficient discharge of the comparator 12, the CPU 3 of the basic unit is initialized, but the CPU 4 of the peripheral device is not initialized, resulting in a malfunction.

[Purpose of the invention]

An object of the present invention is to provide a sequence control device that allows peripheral devices to be attached and detached during power supply.

[Summary of the invention]

The present invention relates to a basic unit and a peripheral device configured to be detachably attached to the basic unit so that when it is attached to the basic unit, power is supplied from the basic unit and data can be exchanged with the basic unit. In the sequence control device, the basic unit includes a first CPU, a first reset circuit that is connected to an AC power supply and generates a signal to reset the first CPU by detecting an instantaneous interruption of the AC power supply. An output terminal connected to the output of the first reset circuit is provided, and the peripheral device has an input terminal connected to the output terminal, a second CPU, and resets the second CPU by detecting its attachment to the basic unit. a second reset circuit that generates a signal to reset the output of the second reset circuit; one of its inputs is connected to the output of the second reset circuit; A logical sum circuit is installed to logically sum the outputs of the two CPUs and supply the output as a reset signal to the second CPU to prevent malfunctions caused by instantaneous AC power interruptions or by attaching or detaching peripheral devices while power is being supplied. It is something.

[Embodiments of the invention]

An embodiment of this description will be described below with reference to FIGS. 5 and 6. The sequence control device consists of a basic unit 1 and peripheral equipment 2.

The basic unit 1 has the same configuration as the conventional one shown in FIG.
It has a reset circuit 5 as a first reset circuit that generates a signal for resetting the circuit. The peripheral device 2 is detachably attached to the basic unit 1 and is configured so that when it is attached to the basic unit 1, power is supplied from the basic unit 1 and data can be exchanged with the basic unit 1. 2
A CPU 4 as a CPU of the basic unit 1, a reset circuit 6 as a second reset circuit that detects a momentary interruption of the power supply supplied from the basic unit 1 and generates a signal to reset the CPU 4, and an output of the reset circuit 6 and a reset circuit 5. It is composed of a two-input OR gate 16 as a logical sum circuit which takes the logical sum of the outputs and supplies the output to the CPU 4 as a reset signal.

Figure 6 shows the waveforms of various parts when there is a momentary interruption of the AC power supply with peripheral equipment installed. That is, if there is a momentary interruption (instantaneous power failure) of one cycle or more in the AC power supply as shown in Fig. 6A, the reset circuit 5 of the basic unit is activated.
operates, and its output is supplied to the reset input terminal of the CPU 3 via an inverting circuit as a signal having the waveform shown in FIG. The CPU 3 is reset at the rising edge of the signal. Output of reset circuit 5 (6th
A signal having an inverted waveform of waveform E in the figure) is supplied to one of the input terminals of the OR gate 16 of the peripheral device 2 via the signal line. The output of the OR gate 16 is supplied to the reset input terminal of the CPU 4 via an inverting circuit.
Therefore, the CPU 4 is also supplied with a signal having the same waveform as shown in FIG. 6 (G), and the CPU 4 is reset at the rising edge of this signal.

Furthermore, waveforms in the peripheral device 4 when the peripheral device 2 is attached while power is being supplied to the basic unit 1 are shown in FIGS. Remove the peripheral device 2 from the basic unit 1 at the timing of removing the peripheral device shown in Figure 6.
If you attach it again at the timing of , basic unit 1
The reset signal (H in the figure) has already been established, but because the power supply to the peripheral device 2 was temporarily cut off, the voltage at the capacitor 12 of the reset circuit 6 temporarily became zero as shown in F in the figure. After installation, the voltage gradually increases with the time constant of the resistor 10 and capacitor 12. The output of capacitor 12 is supplied to the other input terminal of OR gate 16 via a Schmitt circuit. Therefore, as shown in the waveform in Figure 6 (t), the output of the reset circuit 6 becomes LOW when the peripheral device is removed, and becomes Hi when the voltage of the capacitor 12 reaches a predetermined level after the peripheral device is removed. At startup, reset CPU4 and restart. This makes it possible to initialize the CPU 4 of the peripheral device 2 even if a momentary power outage occurs or if the peripheral device 2 is connected or removed while power is being supplied to the basic unit 1.
Malfunctions of the peripheral device 2 can be prevented.

In the above embodiment, the only reference voltage for resetting is the threshold voltage at the input of the Schmitt circuit. Although this embodiment can cope with sudden drops in voltage such as when peripheral devices are connected or removed or when the power supply is momentarily cut off, in the case of a drop in power supply voltage due to load fluctuations, it is possible to deal with sudden drops in voltage due to attachment/disconnection of peripheral devices, momentary interruption of the power supply, etc. In some cases, the power supply voltage repeatedly drops and rises as the load turns on and off.

To solve this problem, the reset circuit of the basic unit consists of an input section, a voltage drop detection section, an output section, and a positive feedback circuit that positively feeds back the signal of the output section to the voltage drop detection section. A modification of this embodiment in which a hysteresis characteristic is provided between the parts is shown in the seventh example.
This will be explained with reference to FIG.

For example, FIG. 7 shows an example of a circuit configuration of a peripheral device using a detection circuit for this purpose. The configuration and operation of this circuit will be explained below.

In this modification, power supply input terminals T ₁ and T ₂ are provided. These input terminals T ₁ and T ₂ are connected to an AC power source 7 in the same way as the basic unit 1 shown in FIG. The voltage V of the AC power supply 7 is rectified and smoothed by a rectifier circuit 120 and a capacitor C ₁ , and then stabilized by a stabilizing IC 101.
A control circuit 1 having an input section, a voltage drop detection section, an output section and a CPU of a reset circuit stabilized by
21 as a constant power supply voltage Vcc.
Further, in this modification, a power supply voltage detection signal 110 is input to the signal input terminal _T3 . In order to detect the power supply voltage, the input terminal T3 is connected to the AC power supply 7 via the DC output side of the rectifier circuit 120 or a rectifier (not shown). In this modification, when the power supply V is turned on, a reset signal is generated for a predetermined time depending on the charging time of the resistor R ₁₀ and the capacitor C ₅ and is output to the CPU of the control circuit 120.

Next, when the power is cut off, the detection signal 110 at terminal T ₃ turns OFF, and the comparison voltage divided by resistors R ₁ and R ₂ becomes lower than the reference voltage divided by resistors R ₃ and R ₄ . Therefore, due to the characteristics of the comparison IC (hereinafter referred to as the comparator), the output of comparator IC ₂ becomes “HI” level and the output of the next stage comparator IC ₃
is input. At this time, since the voltage becomes higher than the reference voltage divided by resistors R ₇ and R ₈ , the output of comparator IC ₃ becomes “LOW” level, and capacitor C ₅ is discharged through resistor R ₉ . Here, the resistor R ₉ is a protection resistor for the comparator IC ₃ , so it may have a small value, so that rapid discharge is possible.

Furthermore, instantaneous power outages and rapid drops in the power supply can be dealt with by selecting the time constants of the capacitor C ₂ and resistors R _{5 and 6} .

By the way, when the detection signal drops due to a drop in the power supply voltage as shown in FIG. 8B, especially in the vicinity of the drop detection, the potential obtained by dividing the drop detection signal by the resistors R ₁ and R ₂ is the voltage at the resistor R _{3 .} , _R4 , a reset signal can be output in the same way as at the time of cutoff, but depending on the control circuit 121, the load is reduced by being reset, and the power supply voltage increases. Therefore, the drop detection signal also rises, and this divided potential becomes slightly higher than the reference voltage, causing the output of comparator IC ₂ to become “LOW” level.
Further, the output of the comparator IC ₃ becomes "HI" level and is charged again by the resistor R ₁₀ and the capacitor C _5. After a predetermined time, the reset signal is released and the control circuit 121 starts operating. Therefore, the load becomes heavy, the power supply voltage decreases, and the above phenomenon repeats as shown in FIG. 8B. This is extremely dangerous if a power load or the like is connected to the control circuit 121. In order to prevent this phenomenon, a comparator IC ₄ and a resistor R ₁₁ are newly provided, and the operation near the drop detection level is as follows.

In other words, if the detection signal voltage (divided voltage of resistors R ₁ and R ₂ ) drops even slightly from the reference voltage caused by resistors R ₃ and R ₄ , the output of comparator IC ₂ becomes “HI”, and the reference voltage of comparator IC ₃ (resistance (divided voltage of R ₇ and R ₈ ), and the output of comparator IC ₃ becomes “LOW”. Therefore, capacitor _C5 is rapidly discharged and a reset signal 111 is output.

At the same time, positive feedback is performed by comparator IC ₆ , and the comparison voltage that is the drop detection signal becomes smaller than the reference voltage (divided voltage of resistors R ₇ and R ₈ ).
The output of comparator IC ₄ becomes “LOW”.

Therefore, the voltage of the drop detection signal 110 is
The voltage is divided by the parallel resistances R ₂ and R ₁₁ and the resistor R ₁ .

That is, since the resistance value in the parallel resistance circuit is smaller than the value in the case of a single resistor circuit, the value obtained by dividing the drop detection signal voltage also becomes smaller.

As a result, the reset signal is kept stable even if a slight change occurs in the detection signal because the potential is lower than the potential at which the drop was initially detected.

Next, when the power supply voltage rises to a voltage within a predetermined range, the drop detection signal voltage also rises, and the divided potential at the parallel resistors R ₂ and R ₁₁ and the resistor R ₉ also rises. When the voltage becomes higher than the reference voltage (resistors R ₃ and R ₄ ), the output voltage of comparator IC ₂ becomes "LOW" and the output of comparator IC ₃ becomes "HI", so that the discharge is caused by resistor R ₁₀ and capacitor C ₅ . The reset signal is released a predetermined time after the start. This situation is shown in FIG. 8A.

As described above, the control circuit 1 provides a hysteresis characteristic to the drop detection and provides a stable reset signal even if there is a slight change in the drop detection signal due to load fluctuation.
It can be output to 21.

Now, in the embodiment shown in Fig. 7, positive feedback is provided to the drop detection signal, but a positive feedback circuit that increases the reference voltage using resistors R ₃ and R ₄ may be configured, and this can be used. The same effect can be obtained even if

Further, although the power supply circuit is omitted in the embodiment shown in FIG. 7, the same effect can be obtained with either an AC power source or a DC power source.

Furthermore, it can be applied not only to reset circuits but also to memory protection circuits and the like.

According to this embodiment, even if the power supply voltage drops to a voltage close to the drop detection level for a long time and the load fluctuates, the reset signal can be reliably output, so the control circuit 121 can be extremely safely protected. There is an effect that can be done.

〔Effect of the invention〕

According to the present invention, even if the power supply to at least one of the basic unit or peripheral devices is temporarily interrupted, the CPU of the peripheral device can always be reset after power is restored, and the peripheral devices can be connected or removed while power is being supplied to the basic unit. Accordingly, it is possible to obtain a highly reliable sequence control device in which malfunctions can be prevented even when

[Brief explanation of the drawing]

1 and 3 are block diagrams of conventional sequence control devices, FIGS. 2 and 4 are waveform diagrams showing voltage waveforms at various parts in FIGS. 1 and 3, and FIG. FIG. 6 is a waveform diagram showing the waveforms of each part of the sequence control device in an embodiment of the present invention, and FIG. 7 is a block diagram of the basic unit in a modification of the embodiment of the present invention. FIG. 8A is a waveform diagram showing the reset signal output waveform of the circuit of FIG. 7, and FIG. 8B is a waveform diagram showing the reset signal output waveform in the conventional example. 1...Basic unit, 2...Peripheral equipment, 3...
Basic unit CPU, 4...Peripheral device CPU, 5...
... Basic unit reset circuit, 6 ... Peripheral device reset circuit, 7 ... AC power supply, 8 ... Comparator, 9, 12 ... Capacitor, 10, 11, 14
...Resistor, 13...Diode, 16...OR
Gate.

Claims (1)

[Scope of Claims] 1. A basic unit, which is configured to be detachably attached to the basic unit, and when attached to the basic unit, power is supplied from the basic unit and data can be exchanged with the basic unit. In a sequence control device consisting of peripheral devices configured as such, the basic unit is connected to a first CPU and an AC power supply, detects a momentary interruption of the AC power supply, and operates the first CPU.
The peripheral device includes a first reset circuit that generates a signal to reset the CPU, and an output terminal connected to the output of the first reset circuit, and the peripheral device has an input terminal connected to the output terminal, and a second reset circuit. a second reset circuit that detects attachment to the basic unit and generates a signal to reset the second CPU; one of its inputs is connected to the output of the second reset circuit;
The other input is connected to the input terminal and the second input terminal is connected to the second input terminal.
1. A sequence control device comprising: an OR circuit which logically sums the output of the first reset circuit and the first reset circuit, and supplies the output as a reset signal to the second CPU.