JPH0334689B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a reset signal generating device, which reads information from a memory element in which a program procedure is written in, for example, a microcomputer.
The present invention relates to a reset signal generating device that resets an arithmetic circuit that decodes this signal and performs a predetermined operation to an initial operating state at the end of a power outage.

[Prior art]

A conventional device of this type is shown in FIG. FIG. 1 is an electrical wiring diagram showing a conventional reset signal generating device. In FIG. 1, a series circuit of a resistor 1 and a capacitor 2 is connected between a power supply terminal 3 and ground. Diode 4 is resistor 1
The capacitor 2 is connected in parallel with the capacitor 2 to discharge the charge stored in the capacitor 2 during a power outage. A reset terminal 5a of the central processing unit (hereinafter referred to as CPU) 5 is connected to a resistor 1.
and the connection point between the capacitor 2 and the capacitor 2.

Next, this operation will be explained using FIG. 2. Second
FIG. 2A is a time chart of the voltage waveform applied to the power supply terminal 3, and FIG. 2B is a time chart of the charging voltage waveform of the capacitor 2. Now, when a power outage occurs at time t ₁ shown in Figure 2 a and b, the voltage applied to the power supply terminal 3 decreases from time t ₁ as shown in Figure 2 a, and finally at time t ₃ .
Reach OV. Therefore, the charging voltage of capacitor 2 also starts to decrease from time t ₁ as shown in FIG. 2b,
The reset level V _R is reached at time t ₂ and OV is reached at time t ₄ . When the reset level V _R is reached at time _t2 , the CPU 5 enters the reset state since this voltage is the input voltage of the reset terminal 5a.

Next, when the power outage is restored at time _t5 , the voltage applied to the power supply terminal 3 rises again as shown in _{FIG .}
reach. On the other hand, the charging voltage of the capacitor 2, which is the input voltage of the reset terminal 5a, also rises at time _t5 as shown in _FIG . Reached at ₇ . Therefore, since there is a difference between time _t6 and time _t7 , the CPU 5 is reset using this delay time T.

However, with conventional equipment, the reset level
If it is not possible to adjust the _V There was a drawback that it was not possible to reset the CPU5. For this reason, CPU5
It is not possible to start operation from the normal initial state, resulting in a so-called runaway, and this has the drawback of causing great damage to the controlled object, especially when a microcomputer circuit is used as a control device.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above. For example, a power failure in a microcomputer circuit is detected, and a monostable multivibrator is triggered at the rising edge when the power failure state is recovered. This circuit converts it into a pulse signal of a fixed time, and resets the CPU by ORing this pulse signal with the delayed signal of the power failure detection signal, thereby reliably resetting the CPU.
The object of the present invention is to provide a reset signal generating device that inhibits the occurrence of a CPU runaway phenomenon.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is an electrical wiring diagram showing an embodiment of the reset signal generating device of the present invention. In FIG. 3, a series circuit of variable resistor 11 and resistors 12 and 13 is connected between power supply terminal 14 and ground,
It divides the voltage of the microcomputer circuit. The voltage comparison circuit 15 compares the reference voltage with the voltage of the microcomputer circuit, and produces an output B of H level when the voltage of the microcomputer circuit is higher than the reference voltage, and outputs L level when it is less than the reference voltage. Its input terminal (IN) is connected to the connection point between resistor 12 and resistor 13, and its input terminal (HYS) is at the power failure detection level shown in Figure 4A.
In order to provide hysteresis between V ₁ and a slightly higher power recovery detection level V ₂ , it is connected to the connection point between resistors 12 and 13 via a resistor 16 . In the monostable multivibrator 17, the output B of the voltage comparator circuit 15 is input to the input terminal T, and the output B
It is triggered by the rising edge of , and outputs an L-level pulse output C having a pulse width determined by the time constant of the resistor 18 and capacitor 19 to the output terminal. The delay circuit 20 delays the output B of the voltage comparison circuit 15. The logic circuit 21 is, for example, an OR circuit that inputs an L level signal and outputs an L level signal, and connects the output of the delay circuit 20 and the monostable multivibrator 17.
The logical OR with the pulse output C of the first
This is input to the reset terminal 5a of the CPU 5 of the microcomputer shown in the figure.

Next, this operation will be explained using FIGS. 4A to 4E. 4A is a time chart of the power supply voltage of the microcomputer circuit input to the power supply terminal 14, FIG. 4B is a time chart of the output B of the voltage comparison circuit 15, and FIG. Time chart of pulse output C, 4th
FIG. D is a time chart of the output of the delay circuit 20. FIG. 4E is an output time chart of the logic circuit 21. Now, at time _t1 in FIG. 4A, the power supply voltage of the microcomputer circuit input to the power supply terminal 14 decreases, and when it drops to the power failure detection level _V1 at time _t2 , the voltage comparator circuit 15
operates, and its output B becomes the L level, which is the power failure detection level _V1 , at time _t2 , as shown in FIG. 4B. Then the supply voltage is restored at time t ₃ ,
When the power restoration detection level V ₂ is restored at time t ₄ ,
The output B of the voltage comparison circuit 15 returns to the H level at time t4, as shown in FIG. _4B . As shown in FIG. 4C, the output pulse C of the monostable multivibrator 17 is triggered by the rising edge of the output B at time _t4 and becomes L level. The width of this L level is determined by the time constant of the resistor 18 and capacitor 19, and after the pulse time has elapsed, the signal becomes H level at time _t5 .

Similarly, as shown in FIG. 4A, the voltage decreases to power failure detection level V ₁ at time points t ₆ and t ₁₀ and recovers to power restoration detection level V ₂ at time points t ₈ and t ₁₃ . Accordingly, as shown in FIG. 4B, the output B goes to the L level at times t ₆ and t ₁₀ and returns to the H level at the times t ₈ and t _13. Here, the output B of the voltage comparison circuit 15 Only the reset terminal 5 of the CPU 5 is shown in Figure 1.
If the power outage is extremely short, the output waveform of the output B of the voltage comparator circuit 15 will also be extremely short, and the pulse width necessary for resetting the CPU 5 may not be secured. To prevent this, a monostable multivibrator 17 is provided, and by appropriately selecting the values of the resistor 18 and capacitor 19, the pulse width of the L-level pulse output C can be set as a reset signal. It is possible to secure a pulse width greater than the required pulse width.

That is, without the monostable multivibrator 17, between times _t2 and _t4 and between times t6 and _t6 shown in FIG. 4B.
By the output B of the short voltage comparator circuit 15 during _t8 ,
CPU5 is not reset. However, at times t ₄ and t ₈ the monostable multivibrator 17
The output pulse C is triggered to the L level as shown in FIG. 4C, and remains at the L level until time points _t5 and _t9 . Further, the output B of the voltage comparison circuit 15 is delayed by the delay circuit 20 as shown in FIG. 4D. Therefore, the logic circuit 21 outputs the output of the delay circuit 20 and the output C of the monostable multivibrator 17, and determines the timings t ₂ to _{t 5} and t ₇ to t ₉ as shown in FIG. 4E. produces an output with a pulse width between sufficiently
It produces an output with a pulse width that can trigger the CPU5.
In this case, since there is a certain time delay from the rise of the output B to the generation of the pulse output C, if the operating speed of the logic circuit 21 is fast, the output of the logic circuit 21 shown in FIG. Although there is a possibility that a waveform may appear, this fear is eliminated because the delay circuit 20 is provided.

Furthermore, as shown between time points _t2 and _t4 and between time points _t6 and _t8 , if the power outage time is short, the circuit voltage will be as shown in Figure 4A.
As shown in Figure 2, the voltage often does not drop to OV and remains within the operating voltage of the IC. On the other hand, if the power outage is long as shown between time points _t10 and _t13 , the circuit voltage will be
As shown in Figure A, it drops to OV. In any of these cases _{, the fourth}
At the rise of output B shown in Figure B, in order to reset the CPU 5 and ensure it is in the initial state,
It is possible to prevent the CPU5 from running out of control.

In the above embodiment, the power failure detection level can be adjusted by adjusting the variable resistor 11 and the resistor 16.
Hysteresis of V ₁ and power recovery detection level V ₂ can be adjusted. Furthermore, due to the action of the delay circuit 20, both the rising and falling edges of the delayed waveform shown in FIG _.
Even if it is detected, it will be delayed by the signal delay time to reach the OR circuit 21, and when the actual circuit voltage falls further below the power failure detection level _V1 , the CPU 5
It is supposed to output a reset signal. Therefore, it is necessary to adjust the power failure detection level V ₁ to a slightly higher value using the variable resistor 11. In order to eliminate the need for this adjustment, the delay circuit 20 needs to be a circuit that delays only the rising waveform.

〔Effect of the invention〕

As described above, according to the present invention, the delayed output of the voltage comparator circuit and the output of the monostable multivibrator that is triggered by the rising edge of the output of the voltage comparator circuit and outputs a pulse signal with a sufficient time width necessary for resetting the CPU. is input into the logic circuit, and this output is
Since it is configured to be supplied to the reset terminal of the CPU, it is possible to secure a reset signal with the necessary time width even in the case of a short power outage, and also to be able to reliably perform a reset even in the case of a long power outage. It has the effect of resetting the CPU.

[Brief explanation of drawings]

Fig. 1 is an electrical wiring diagram showing a conventional reset signal generating device, Fig. 2 a and b are operation explanatory diagrams of Fig. 1,
FIG. 3 is an electrical wiring diagram showing one embodiment of the reset signal generating device of the present invention, and FIGS. 4A to 4E are diagrams explaining the operation of FIG. 3. In the figure, 5 is the CPU, 5a is the reset terminal,
11 is a variable resistor, 12 and 13 are resistors, 14 is a power supply terminal, 15 is a voltage comparison circuit, 16 is a resistor, 1
7 is a monostable multivibrator, 18 is a resistor, 1
9 is a capacitor, 20 is a delay circuit, and 21 is a logic circuit.

Claims (1)

[Claims] 1. Monitoring the input voltage A to the circuit and controlling the input voltage A.
a voltage comparison circuit that generates an output B when the input voltage A becomes below a power failure detection level, and terminates the output B when the input voltage A reaches a power recovery detection level that is higher than the power failure detection level; an output B of the voltage comparison circuit; a monostable multivibrator that is triggered at the end point and generates a pulse output C of a predetermined time width that is longer than the time width required to reset the circuit; a delay circuit that delays the output B of the voltage comparator circuit and generates the output D; and a logic circuit that calculates the logical sum of the output D of the delay circuit and the pulse output C of the monostable multivibrator and outputs a reset signal that resets the state of the circuit to the initial state. Reset signal generator.