JPH0157810B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reset circuit for a logic device comprising a plurality of logic circuits each having a terminal for outputting a pulse signal during normal operation and a reset terminal for initializing the operation. .

Conventionally, a device having a plurality of logic circuits is configured to provide an independent failure detection circuit for each logic circuit, detect abnormal operation of the logic circuit, and reset only the corresponding logic circuit. However, since each logic circuit must operate in conjunction with other logic circuits, in order to restore normal operation of the device, it is necessary for the logic circuit to know the operating state before the failure occurred through restart processing after a reset. It was hot. For this reason, control has become complicated, and the amount of programs in program control logic circuits has increased.

In order to solve the above-mentioned drawbacks, the present invention is configured so that even if one logic circuit becomes abnormal, a plurality of related logic circuits are reset all at once using a simple fault detection circuit. The configuration is such that the reset is repeated until normal operation starts, and the reset operation causes these related logic circuits to resume operation from the initial state all at once.
This eliminates the need for a special restart processing program.

FIG. 1 shows an embodiment of the invention, in which interrelated logic circuits 1 ₁ , 1 ₂ and 1 ₃ each have a pulse output terminal TF and a reset terminal RE. The pulse output terminal TF periodically outputs a pulse train while the logic circuit is operating normally, and in this example, the output pulse has a period of T ₁ (for example, 10 ms).
is almost always at a high level “H”, and the pulse width
During T ₂ (for example, 5 μs), it is at a low level “L”.
When a low level is applied to the reset terminal RE, the logic circuit is reset, and at that time, the pulse output terminal TF of the logic circuit becomes a high level "H". Thereafter, when the reset terminal RE becomes high level "H", the logic circuit is initialized and starts operating.

Fault detection circuits 2 ₁ to 2 ₃ are connected to pulse output terminals TF of each logic circuit _{1 1} to 1 ₃ , respectively. These fault detection circuits 2 ₁ to 2 ₃ detect when the input pulse disappears, and in this example, they are composed of monostable multivibrators 3 ₁ to 3 ₃ , and the input terminal D of the multivibrator is The output of the corresponding pulse output terminal TF is applied, and it is triggered at the rising edge of the output and outputs a pulse with a constant width.
The width T ₆ of each output pulse of these monostable multivibrators 3 ₁ to 3 ₃ is longer than the output pulse period T ₁ of the pulse output terminal TF, and is set to, for example, 40 ms.

If a fault is detected from any of these fault detection circuits 2 ₁ - 2 ₃ , the related logic circuits 1 ₁ - 1 ₃ are reset. For this purpose, a reset signal generating circuit 11 is provided. The reset signal generation circuit 11 includes monostable multivibrators 4 1 _to 4 ₃ corresponding to the fault detection circuits 2 ₁ to 2 ₃ , respectively, and the monostable multivibrator is connected to the input terminal D of these monostable multivibrators 4 ₁ to 4 ₃ . 3 ₁ to 3 ₃ outputs are given, and it is triggered at the rising edge of the pulse and outputs a relatively short pulse with a constant width, for example, 1 ms. The Q outputs of these monostable multivibrators 4 ₁ to 4 ₃ are connected to npn transistors 5 ₁ to 5 through resistors, respectively.
5 Supplied to each pace of ₃ . The emitters of these transistors 5 ₁ to 5 ₃ are grounded, and the collectors are connected wired to each other and grounded to the respective reset terminals RE of the logic circuits 1 ₁ to 1 ₃ and connected to the positive power supply terminal 13 through a resistor 12. has been done. The connection point between the resistor 12 and the collector is grounded through the collector emitter of the transistor 14.

This transistor 14 is for generating an initial reset signal at startup, and the output of a power-on reset generation circuit 15 is applied to the base of the transistor 14 through an inverter 16. In the circuit 15, the power terminal 13 is grounded through the resistor 17 and the capacitor 18, and the connection point between the resistor 17 and the capacitor 18 is supplied as the output of the circuit 15 to the inverter 16.

Monostable multivibrator 3 ₁ ~ _{3 3} and 4 ₁ ~
4 ₃ is a retriggerable circuit, and for a single pulse as shown in Fig. 2A, a retriggerable circuit is set in advance by the rising edge of the input terminal D as shown in Fig. 2B. Outputs a pulse with a time width.
The Q outputs of these multivibrators become "H" during the pulse output period, and the outputs are the inverted outputs. If the input to terminal D is a pulse train whose period is shorter than the output pulse width as shown in Figure 3A, it will be retriggered at each rising edge of each input pulse, and when the pulse input stops for more than the set time. Then, the output returns to its original state as shown in FIG. 3B.

The logic circuit _1-3 shows _an example in which reset is applied _repeatedly until restarting when a fault is detected. The AND circuit 19 performs a logical product with the output of the monostable multivibrator 33, and the output thereof is applied to the input terminal D of the monostable multivibrator ₃₃ .

The operation of the reset circuit of the present invention in various modes will now be described.

A When the power is turned on When the power is turned on at time _t1 as shown in Fig. 4A, the capacitor 18 of the power-on reset generating circuit 15 in Fig. 1 is gradually charged, and the output of the circuit 15 becomes an integral waveform. stand up. When the output of the circuit 15 exceeds a certain potential, the output of the inverter 16 becomes a low level "L" at time _t2 , as shown in FIG. 4B.
This changes the transistor 14 from a conductive state to a cut-off state. On the other hand, when the power is turned on, each output of the monostable multivibrators 4 ₁ to 4 ₃ is at a low level "L" and the transistors 5 ₁ to 5 ₃ are in a cut-off state. Therefore, the output of the reset signal generating circuit 11 changes from the low level "L" to the high level "H" as shown in FIG. 4C, causing the logic circuits ₁₁ to ₁₃ to operate all at once from the reset state. As a result, the logic circuit ₁₁ , for example, sends out a pulse train from its terminal TF as shown in FIG. 4D, and the output of the fault detection circuit ₂₁ becomes low level "L" as shown in FIG. The output of vibrator ₄₁ is shown in Figure 4F.
The signal is stored as a low level “L” as shown in FIG.

B. When the logic circuit 1 ₁ stops operating The logic circuit 1 ₁ stops operating and no pulses are sent to the output terminal TF from time t ₁ as shown in FIG. 5A. As a result, the monostable multivibrator 3 ₁ in the fault detection circuit 2 ₁ is restored at time t ₂ after time T ₃ as shown in FIG. 5B, and its output becomes a high level "H". This triggers the monostable multivibrator 4 ₁ and its output Q becomes high level "H" for a time T ₄ as shown in FIG. 5C. During this period, the transistor ₅₁ becomes conductive, and the reset signal generating circuit 11 goes to the low level "L" for the time _T4 , as shown in FIG. 5D, and then goes to the high level "H" again. Therefore all logic circuits 1
₁ to ₁₃ are reset and the operation starts again from the initial state.

When the above reset operation is completed normally, a pulse train is sent out again from the pulse output terminal TF, and the output of the fault detection circuit ₂₁ becomes low level "L" again at time _t3 as shown in FIG. 5B, indicating normal operation. It is in operation mode. However, if the reset operation is not performed normally, the output of the fault detection circuit ₂₁ is held at a high level "H" and the restart operation of the logic circuit ₁₁ is no longer performed.

C When the operation of logic circuit 1 ₃ stops As shown in FIG. 6A, when logic circuit 1 ₃ stops operating and stops outputting pulses from time t ₁ , the
Similarly to the operation in the figure, an output is generated from the fault detection circuit ₂₃ at time _t2 as shown in Figure 6B, and a pulse is generated from the output of the monostable multivibrator ₄₃ as shown in Figure 6C. Then, a reset pulse is generated as shown in FIG. 6D. Since the input of the monostable multivibrator ₃₃ is given the logical product of the output of the pulse output terminal TF and the reset pulse, the monostable multivibrator ₃₃ is triggered at the rising edge of the reset pulse and its output is shown in Figure 6B. As shown at time _t3 , it becomes low level "L".
Therefore, if the reset operation is not performed normally, the same reset operation as described above is repeated again when the monostable multivibrator ₃₃ is restored as shown by the dotted line at time _t4 in FIG. 6B.

In FIG. 1, the outputs of the monostable multivibrators 4 ₁ to 4 ₃ have a wired-OR logic via transistors 5 ₁ to 5 ₃ .
It is also possible to configure using logic gates.

As explained above, according to the present invention, a plurality of logic circuits can be reset all at once using a simple fault detection circuit. Particularly in small-scale systems, there is little demand for restoring the operation before the failure even in the event of a failure, so the present invention is of great significance as it allows the system to be reset with a simple configuration.

Furthermore, according to the circuit shown in case B above, if a logic circuit that does not affect the system operation cannot be recovered by being reset once, it can be disconnected and the operation can be continued. On the other hand, according to the circuit shown in case C above, the logic circuits essential for system operation are repeatedly reset until they start normal operation. In this manner, the present invention allows these reset circuits to be easily configured depending on the importance of the logic circuit.

[Brief explanation of drawings]

FIG. 1 is a logic circuit diagram showing an embodiment of the present invention, FIGS. 2 and 3 are timing diagrams showing the operation of a monostable multivibrator, FIG. 4 is an operation timing diagram when the power is turned on, and FIG. 5 and FIG. 6 are operation timing charts when the logic circuit is stopped. ₁₁ to ₁₃ : logic circuit, ₂₁ to ₂₃ : fault detection circuit, ₃₁ to ₃₃ , 41 to ₄₃ : monostable multivibrator, ₁₁ : reset signal generation circuit, 15: power-on reset generation circuit , TF: Pulse output terminal,
RE: Reset terminal.

Claims (1)

[Scope of Claims] 1. A logic device comprising a plurality of logic circuits each having a reset terminal for initializing operation and a pulse output terminal for periodically outputting a pulse signal during normal operation, A fault detection circuit is provided corresponding to each of the fault detection circuits and outputs a detection signal when a pulse signal is not input for a certain period of time, and a fault detection circuit is connected to the output side of these detection circuits and outputs a reset pulse when at least one of the detection signals is input. and a reset signal generating circuit that generates a reset pulse and supplies the reset pulse to the reset terminals of all of the above logic circuits, and an AND circuit in which the output pulse of some of the above logic circuits is used as one input, and the reset pulse is used as the other input.
A reset of a logic device, characterized in that a circuit is provided, the output of which is supplied to the input terminal of the corresponding fault detection circuit, and the output pulses of the other logic circuits are directly supplied to the input terminal of the corresponding fault detection circuit. circuit.