JPS6027993Y2 - Power-on device for electrical equipment - Google Patents

Description

[Detailed Description of the Invention] The present invention is designed to power up electrical equipment that has multiple electrical memory circuits that require a delay at startup, such as magnetic recording/reproducing devices, and can select one of these electrical memory circuits with a switch. Regarding equipment.

Conventionally, when extracting a power-on signal from an electric device having an electric memory circuit such as a magnetic recording/reproducing device, the first
As shown in the figure, a capacitor C has one end connected to the 10B power supply and the other end connected to the base terminal of the transistor Tr□ via a resistor R1, and a connection between the capacitor C1 and the emitter terminal of the transistor Tr1. has a diode D1 interposed in the circuit, and generates one pulse having a pulse width corresponding to a time constant determined by the capacitance of the capacitor C1 and the resistance value of the resistor B1 when the 10B power is turned on. Take out one pulse from the power-on pulse generation circuit,
A method is used to set an electrical memory circuit.

On the other hand, many electrical memory circuits do not know whether to enter the set side or the set side when the power is turned on, and in non-operational mode, it is necessary to reset the circuit by sending a pulse to the reset side.

Therefore, in an electrical device having an electrical memory circuit that requires a delay at startup, it is proposed to selectively perform the two operations described above using one pulse output from the power-on pulse generation circuit when the power is turned on. In this case, the electric memory circuit had a configuration as shown in FIG.

Here, the power-on signal is used only for setting in the operating mode of the electrical memory circuit, that is, for applying to the set input, and when the electrical memory circuit is powered on, that is, 10B
When power is applied, the electric memory circuit itself is reset by adding capacitors C2 and C3 as shown in FIG. 3 to the electric memory circuit, in addition to the reset input caused by the stop mode or the like.

In this circuit, increasing the capacitance of capacitors C2 and C3 tends to affect other set inputs and reset inputs, and it is necessary to add capacitors to all electrical memory circuits, which is disadvantageous in terms of cost. Moreover, since the reset circuit must be simplified, the reset level is not certain.

Therefore, in high-end machines that have multiple electrical memory circuits, a changeover switch is used to reset the non-operating mode as shown in FIG. 4, but this requires a complicated wiring system.

An example of this will be explained below based on a magnetic recording/reproducing apparatus as shown in FIG.

1 is a power-on pulse generation circuit.

2 and 3 are first and second slide switches respectively having a recording terminal a, a play terminal and an off terminal C, and the recording terminal a of the first slide switch 2 is connected to the set input of the RFC memory 4, and the play terminal is connected to the set input of the RFC memory 4. The off terminal C is connected to the reset input of the RFC memory 4, the recording terminal a of the second slide switch 3 and the play terminal C are connected to the set input of the PLAY memory 5, and the off terminal is connected to the set input of the PLAY memory 5. Connected to the reset input.

6 and 7 are an F-FWD memory and a REW memory, the reset inputs of which are connected to the power-on pulse generation circuit 1, respectively.

Further, the power-on pulse generating circuit 1 is connected to the respective common terminals of the first and second slide switches 2 and 3.

If the power is turned on with the slide switches 2 and 3 set to the OFF terminal C, all memories will be in the OFF mode since the reset input is supplied.

Next, when the power is turned on with the slide switches 2 and 3 switched to the play terminals, the set input is supplied only to the PLAY memory 5, and the RFC memory 4,)
'-Since a reset input is supplied to the FWD memory 6 and the REW memory 7, the PLAY mode is set.

Furthermore, when the power is turned on with the slide switches 2 and 3 switched to recording terminal a, the RFC
A set input is supplied to memory 4 and PLAY memory 5, and F-FWD memory 6 and REW memory 7
Since the reset input is supplied to REC-PLAY
mode.

In the above configuration, since the first and second slide switches 2 and 3 are usually installed on the front panel of the device,
It is necessary to conduct many wirings from each terminal a''c to the set input and reset input of the memories 4 and 5, which has the disadvantage that the wiring within the device becomes complicated.

In the case of FIG. 4, switches 2 and 3 with two circuits and three contacts are used, but in FIG. 7, a switch 2 with one circuit and three contacts is used. This circuit requires four diodes.

FIG. 9 shows a circuit for play only, and this circuit requires a switch 20 with one circuit and two contacts.

On the other hand, in a magnetic recording/reproducing device, when a coupler of a light-emitting element (lamp) and a light-emitting element (cadmium sulfide element) is used to detect the beginning and end of a tape, for example, it takes a long time before the power-on signal coupler can operate normally. Since it takes time, in order to operate a circuit system including such an element, it is necessary to delay the timing at which the set pulse is generated a little from when the power is turned on.

For example, even if the set pulse enters the PLAY mode, immediately after the power is turned on, the state may be the same as the end detection until the start and end detection operates normally.
Then, I mistakenly entered the terminal in PLAY mode and entered the normal REW mode.

In this REW mode, it is common to prohibit a shift to another mode for a certain period of time, so even if the power-on pulse is lengthened, the play operation will not be activated.

Therefore, in such a case, it is desirable to remain in the reset state for a while after the power is turned on, and then proceed to the play operation with a delay.

By the way, as a conventional method of delaying the timing of the set pulse from when the power is turned on, as shown in FIG.
A method has been used in which the rising edge of the set pulse is blunted by interposing the set pulse, but this has the disadvantage that the output pulse of the set pulse is unstable because the waveform of the set pulse is distorted.

The present invention has been made to solve the above-mentioned drawbacks, and is used in electrical equipment in which the operation of an electrical memory circuit that requires a delay at startup can be selected by switching the electrical memory circuit, without destroying the waveform of the set pulse. It is an object of the present invention to provide a power-on device that can delay the generation of the set pulse from the time of power-on, and simplify switch wiring for selecting an operation by an electric memory circuit.

In order to solve this problem, the present invention includes a switch that is connected to each of a plurality of electrical memory circuits and can set the electrical memory circuit, and a switch that generates a narrow first pulse signal as a power-on signal. a first pulse generation circuit,
A second pulse signal that generates a second wide pulse signal when the power is turned on.
a pulse generation circuit; a reset circuit that resets the electric memory circuit by the first pulse signal; and a reset circuit that resets the electric memory circuit to the reduced diameter of the first pulse signal by the second pulse signal via the switch. It has a set circuit for setting.

Hereinafter, one embodiment of the present invention will be described based on the drawings.

In FIG. 2, one end of each of C11 and C2□ is connected to a 10B power supply, and the other end is connected to a resistor R□1. Capacitors Dll and Dl are connected to the base terminal of the transistor Tr□tt Tr□2 via R□,.

are the capacitors C11, C, respectively.

and transistor Tr11. A diode is interposed between the emitter terminal of Tr1□, R13 and R16 are load resistances, and R□2t and R15 are bias resistances.

11 is the aforementioned power-on pulse generation circuit (Fig. 1)
It has the same configuration effect as the capacitor C1 when the power is turned on.
A first power-on pulse generation circuit that generates a first power-on pulse having a pulse width determined by the capacitance of □ and the resistance value of the resistor R1□; 12 is a second power source whose width is wider than the first power-on pulse when the power is turned on; This is a second power-on pulse generating circuit for extracting the power-on pulse simultaneously with the first power-on pulse.

By the way, the case where the electric memory circuit of the magnetic recording/reproducing apparatus is selectively used by using the circuit that generates two power-on pulses having different pulse widths as described above will be explained with reference to FIG.

In FIG. 5, 11 is the first pulse generator that generates narrow pulses.
In the power-on pulse generation circuit, the first power-on pulse from the first power-on pulse generation circuit 11 is applied as a reset input to each of the RFC memory 15, the PLAY memory 16, );'-FWD memory 17 and the REW memory 18. Supplied.

Reference numeral 12 indicates a second power-on pulse that simultaneously generates a second power-on pulse having a width wider than the first power-on pulse.
This is a power-on pulse generation circuit.

13 and 14 are first and second slide switches respectively having a recording terminal a, a play terminal and an off terminal C; the recording terminal a of the first slide switch 13 is connected to the set input of the RFC memory 15; The recording terminal a and the play terminal of the second slide switch 14 are connected to the set input of the PLAY memory 16.

These slide switches 13 and 14 are interlocked with each other, and their common terminals are connected to the second power-on pulse generating circuit 12.

As you will see, the wiring from the play terminal and off terminal C of the first slide switch 13 to the reset input of the RFC memory 15 is deleted, and the wiring from the off terminal C of the second slide switch 14 to the reset input of the PLAY memory 16 is removed. The wiring to the input has been removed.

Now, if you turn on the power with slide switches 13 and 14 set to off terminal C, RFC memory 15 and P
LAY memory 16, F/FWD memory 17, REW
A reset input is supplied to all memories 18, and the memory 18 is set to OFF mode.

Next, when the slide switches 13 and 14 are set to the play terminals and the power is turned on, the RFC memory 15,
The F-FWD memory 17 and the REW memory 18 are reset by the first power-on pulse, and the PLAY memory 16 is set by the second power-on pulse after the first power-on pulse disappears, so that the PLAY mode is set.

Furthermore, if you turn on the power with the slide switches 13 and 14 set to recording terminal a)'-
The FWD memory 17 and the REW memory 18 are reset by the first power-on pulse, and the REC memory I
J-15 and PLAY memory 16 are set and REC.
Enters PLAY mode.

Fig. 8 corresponds to Fig. 7, and shows a switch 13 with one circuit and three contacts.
This shows the case where the switch 13, the RFC memory 15, and the PLAY memory 1 are used in comparison with the conventional circuit shown in FIG.
The wiring to the reset input of No. 6 can be removed, and one diode is sufficient.

Also, Fig. 10 shows a circuit for play only, and compared to the conventional circuit shown in Fig. 9, this circuit requires only a switch 21 with one circuit and one contact, so leaf switches and reed switches that can only make one contact per circuit, etc. This is very effective when you have to use

As described above, according to the present invention, in an electrical device in which operation by an electrical memory circuit that requires a delay at startup can be selected by switching the electrical memory circuit, the first power-on pulse is used to reset all the electrical memory circuits, A second power-on pulse, which is wider than the first power-on pulse and which occurs simultaneously with the first power-on pulse, is passed through a changeover switch and used to set an electrical memory circuit that requires a delay in start-up after the first power-on pulse disappears. , the timing can be delayed for the set pulse of the electrical memory circuit that requires a delay during activation without destroying the waveform, and the wiring from the changeover switch to the reset input of the electrical memory circuit that requires a delay during activation has been removed. It is possible to effectively prevent the wiring inside the device from becoming complicated.

[Brief explanation of the drawing]

Fig. 1 is a conventional power-on pulse generation circuit diagram, Fig. 2 is a pulse generation circuit diagram showing an embodiment of the present invention, Fig. 3 is a reset priority circuit diagram at power-on in a normal electric memory circuit, and Fig. 2 is a pulse generation circuit diagram showing an embodiment of the present invention. Figures 4 and 7 are wiring system diagrams when switching a magnetic recording/reproducing device that requires delay operation during recording and play using a single pulse output from the circuit shown in Figure 1. Figures 5 and 8 are wiring system diagrams when the pulse generation circuit of the present invention (Figure 2) is used to switch a magnetic recording/reproducing device that requires delay operation during recording and play.
The figure is a circuit diagram for delaying the timing of a conventional power-on pulse, and Figure 9 is a main part of a switching circuit when a single pulse is used to switch a magnetic recording/reproducing device that requires a delay operation during play. FIG. 10 is a circuit diagram of a main part of a switching circuit when the pulse generating circuit of the present invention is used to switch a magnetic recording/reproducing device that requires a delay operation during play. 11...First power-on pulse generation circuit, 12.
...Second power-on pulse generation circuit, 13, 14.
...Slide switch, 15...REC
Memory, 16...PLAY memory, 17.
...);'-FWD memory 18...
REW memory

Claims (1)

[Scope of utility model registration request] A switch that is connected to each of a plurality of electrical memory circuits and can set the electrical memory circuit; a first pulse generating circuit that generates a narrow first pulse signal as a power-on signal; and a switch that generates a narrow first pulse signal when the power is turned on; a second pulse generation circuit that generates a second pulse signal; a reset circuit that resets the electrical memory circuit with the first pulse signal; and a reset circuit that resets the electrical memory circuit with the second pulse signal; A power-on device for electrical equipment, comprising a set circuit that sets the circuit after the first pulse signal disappears.