JPH0351783Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a timer standby circuit that performs reliable timer operation without requiring a CR-based differentiator circuit.

(Prior Art) In recent years, with the rapid development of electronic technology, various modes of tape decks, for example, are being controlled by integrated deck control circuits.

Such an integrated deck control circuit has non-lock type stop, play, fast forward, rewind, and
The system automatically performs actions corresponding to the operation of the recording and pause switches.

With such a deck control circuit, it is also possible to perform recording or playback at a desired time, for example, and a timer standby circuit is combined to allow this to occur.

Figure 1 shows an example of such a deck control circuit.The deck controller A has non-lock type mode switches MS between each mode input terminal IN1 to IN6 and the power supply +B.
1 to MS6 are interposed. When any of these mode switches MS1 to MS6 is closed,
"H" level signals are supplied to the corresponding input terminals IN1 to IN6. As a result, the deck controller A drives a solenoid and a motor (not shown) for moving the head base to perform the setting corresponding to the selected mode.

On the other hand, the timer standby circuit includes a differentiating circuit consisting of a capacitor C1 and a resistor R1 for differentiating the rise of the power supply +B, and the differential output from this differentiating circuit is sent to the deck controller A via diodes D1 and D2 for preventing backflow. It consists of a timer mode select switch SW that selectively supplies the signal to the playback input terminal IN2 or the recording input terminal IN5.

Note that in the figure, R2 and C2 indicate a resistor and a capacitor, respectively, and these constitute an integrating circuit. In addition, the path for power supply +B is
Contact points of a timer circuit (not shown) are provided.

Then, when a predetermined time is reached, the contacts of the timer circuit are closed and a drive current is supplied from the power supply +B, and a differentiation circuit consisting of a capacitor C1 and a resistor R1 generates a differential pulse at the time when the power supply +B rises. Occur. This differential pulse is then activated by the timer mode select switch.
Diode D1 or D2 selected by SW
Playback input terminal IN of deck controller A via
2 or the recording input terminal IN5.

(Problem to be solved by the invention) However, in the conventional deck control circuit described above, the deck controller A is connected to the power supply +B
Initial reset is performed by the outputs of the integrating circuits R2 and C3, which operate at the rising edge of the signal. Therefore, in the timer standby circuit, it is necessary to generate a differential pulse longer than this reset period.

However, in general, the output pulse width of a CR-based differentiator circuit varies widely depending on various conditions, making control by the timer standby circuit unstable. Furthermore, in order to obtain a differential pulse with a wide pulse width, a capacitor with a large capacity is required, and a differential circuit that requires a capacitor is not suitable for integration.

Furthermore, in the conventional deck control circuit described above, the differential pulse generated when the power is turned on is supplied to the playback or recording mode input terminal IN2 or IN5 of the deck controller A selected by the timer mode select switch SW. ing. Therefore, malfunctions may occur depending on the mode state before the power is turned on.

The present invention has been developed in response to these circumstances, and an object of the present invention is to provide a timer standby circuit that can reliably perform timer mode operation and is suitable for integrated circuits.

(Means for Solving the Problems) In order to achieve the above object, the timer standby circuit of the present invention is equipped with a deck controller for operating the deck mechanism of the deck body in accordance with the selected mode, and also includes a timer standby circuit. In a timer standby circuit that instructs the playback or recording mode corresponding to the switching state of the switch, the first standby circuit is set when the reset signal that rises after the initial reset of the deck controller matches the output of the timer mode select switch. a latch circuit LT2, a gate that sends a playback or recording control signal to the deck controller based on the match between the set output of the first latch circuit LT2 and the output of the timer mode select switch; The present invention is characterized in that it includes a second latch circuit LT1 that is set when the deck mechanism enters a playback or recording mode and resets the first latch circuit LT2.

(Function) In the timer standby circuit of the present invention, when a preset time is reached, the power to the deck body is turned on. At this time, first, the first latch circuit enters the set state when the reset signal that rises after the completion of the initial reset of the deck controller and the output of the timer mode select switch match. The gate then sends a playback or recording control signal to the deck controller depending on the match between the set output of the first latch circuit and the output of the timer mode select switch. This puts the deck mechanism into playback or recording mode. Thereafter, the second latch circuit is set when the deck mechanism enters the playback or record mode, causing the first latch circuit to be reset.

Therefore, after the initial reset operation of the deck controller is completed, the deck controller
After the playback or recording control signal is output to the deck mechanism and the deck mechanism enters the playback or recording mode, the output of the playback or recording control signal can be stopped.

Further, the first and second latch circuits, etc. can be constructed using semiconductors.

(Example) Hereinafter, details of an example of the present invention will be described based on the drawings.

FIG. 2 shows an embodiment of the timer standby circuit of the present invention.

As shown in the figure, the timer standby circuit is equipped with a timer mode select switch SW, the common terminal of which is connected to the power supply +B. Pull-down resistors R3 and R4 are connected to the playback and recording output terminals a and c of this timer mode select switch SW, respectively.

An OR gate G1 is connected to each of the playback and recording output terminals a and c, and receives signals P and R sent from the playback and recording output terminals a and c of the timer mode select switch SW.

One input end of a NAND gate G6 is connected to the output end of the OR gate G1. The output end of the NOR gate G5 is connected to the other input end of the NAND gate G6.

On the output side of the NAND gate G6, there is a first latch circuit LT2 which uses its output as a set input and also uses the output of the NOR gate G5 as a reset input.
is connected. The latch circuit LT2 is INV.−
It is composed of OR gates G7 and G8.

An AND gate G9 is connected to the latch circuit LT2, which inputs the set output Q2 and the output signal P of the timer mode select switch SW, and outputs the reproduction control signal PC to the deck controller (not shown) when these match. ing. The latch circuit LT2 also has its set output Q2.
and the output signal R of the timer mode select switch SW are connected to an AND gate G10 which outputs a recording control signal RC to a deck controller (not shown) when they match.

The input side of NOR gate G5 has a set output Q1.
A second latch circuit LT1 outputs an inverted initial reset signal RST, and an inverter outputs an inverted initial reset signal RST.
TIN is connected. The latch circuit LT1 is a circuit which uses the output of the NAND gate G2 as a set input and also uses the initial reset signal RST as a reset input, and is constituted by two INV.-OR gates G3 and G4. Note that B in the figure indicates an operation confirmation signal for confirming that the tape deck (not shown) is operating in the playback or recording mode.

FIG. 4 shows a state in which the timer standby circuit TSS having such a configuration is connected to the deck controller A, and parts common to those in FIG. 1 are given the same reference numerals.

Next, the operation of the timer standby circuit having such a configuration will be explained using FIG. 3.

First, with the timer mode select switch SW switched to the playback output terminal a side, for example, the timer switch (not shown) is switched to the time t.
1, the power supply +B rises as shown in FIG. 3a. Simultaneously with the rise of the power supply +B, an initial reset operation of the deck controller A is performed by an integrating circuit consisting of a resistor R2 and a capacitor C2. When this initial reset operation is completed, the reset signal RST rises as shown in FIG. 3b. Reset signal RST is inverter IN
When the signal is inverted and then supplied to NOR gate G5, its output becomes "H" level.

On the other hand, since the ORGADE G1 inputs the reproduction output P of the timer mode select switch SW and outputs the "H" level, the output of the NANDGADE G6, which inputs the outputs of the ORGADE G1 and NORGADE G5, goes to the "L" level. becomes. This results in
The latch circuit LT2 is set by the "L" level output of the NAND gate G6, and its set output Q
2 rises as shown in FIG. 3c. Set output Q
2 is inverted to “H” level, AND gate G
Since the inputs of 9 match, the playback control signal PC is supplied to the deck controller A. When the control to the reproduction mode is completed, the operation confirmation signal B is supplied as an "H" level pulse-like signal as shown in FIG. 3d. When the operation confirmation signal B is supplied, the output of the NAND gate G2 goes to the "L" level, and the latch circuit LT1 is accordingly set, so that the set output Q1 rises as shown in FIG. 3e. When the set output Q1 rises, the output of the NOR gate G5 goes to the "L" level, so the latch circuit LT2 is reset and the set output Q2 goes to the "L" level.
Flip to level. Along with this, and gate G
The reproduction control signal PC sent from 9 is also inverted to "L" level.

Therefore, the reproduction control signal PC sent from the AND gate G9 is as shown in FIG.
It is a pulse-like signal that is at "H" level during the period from the rising edge of the RST signal to the rising edge of the operation confirmation signal B. And in this state, the power supply +B is
The latch circuit LT1 is not reset until it is turned OFF, and its state continues to be maintained, thereby preventing malfunctions.

Subsequently, when the timer mode switch SW is set to the recording output terminal C side, during the setting period of the latch circuit LT2, the recording control output RC is sent out from the AND gate G10 as in the case described above. Furthermore, the timer mode select switch SW
When set to the output end b side, the AND gate G
Since no output is supplied to G9 and G10, even if the timer switch operates, control to playback or recording mode is not performed.

In this way, in this embodiment, after the initial reset operation of the deck controller is completed,
Since the transmission of the playback or recording control signal is started, the transmission is ended by the operation confirmation signal, and the operation is locked until the initial reset signal is supplied again, the timer mode operation can be performed reliably. be exposed. Furthermore, when the operation confirmation signal B is generated, the second latch circuit LT1 is set,
Using the set output, the first latch circuit LT2
Since the circuit is configured to reset, malfunctions due to noise or the like are reliably prevented. Furthermore, since circuits such as logic circuits that can be constructed using semiconductors are used, integration is also possible.

(Effects of the invention) As explained above, according to the timer standby circuit of the invention, after the initial reset operation of the deck controller is completed, a playback or recording control signal is output to the deck mechanism, and the deck mechanism starts playing or recording. Since the output of the playback or recording control signal is stopped after entering the recording mode, the timer mode operation can be performed reliably. Furthermore, since the first and second latch circuits can be constructed using semiconductors, they can also be integrated.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional timer standby circuit, Fig. 2 is a circuit diagram showing an embodiment of the timer standby circuit of the present invention, and Figs. 3 a to f are diagrams showing operating waveforms of each part of the circuit. , Figure 4 shows the timer standby circuit shown in Figure 2. ，
R4...Resistance.

Claims (1)

[Claims for Utility Model Registration] A timer standby circuit is provided with a deck controller for operating the decking mechanism of the deck body in accordance with the selected mode, and also instructs a playback or recording mode corresponding to the switching state of the timer standby switch. a first latch circuit LT2 that is set by a match between a reset signal that rises after the initial reset of the deck controller and the output of the timer mode select switch; and a set output of the first latch circuit LT2 and the timer. a gate for sending a playback or recording control signal to the deck controller in accordance with the output of the mode select switch; and a gate that is set when the deck mechanism enters the playback or recording mode based on the playback or recording control signal; A timer standby circuit comprising a second latch circuit LT1 that resets the first latch circuit LT2.