JPS6035306Y2 - Mode control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mode control circuit suitable for a tape deck or the like in which mode selection is performed by an electronic circuit.

Conventional tape deck mode control circuits were activated by applying a trigger signal created by differentiating the falling part of the muting control signal generated when the power was turned on to a transistor connected in parallel to the operating signal. .

In such a conventional mode control circuit, since a differentiating circuit is used, there is a factor of instability in the output, and it is not possible to determine whether or not a predetermined output has been generated.

Furthermore, since a capacitor is used in the differential circuit, it is difficult to integrate the electronic control circuit.

In view of these conventional drawbacks, the present invention operates by changing the level of the input signal of a timer start control circuit that utilizes the fall of the muting signal when the tape deck is powered on, and stops the control output when a predetermined operation is completed. ,
It is an object of the present invention to provide a mode control circuit which prevents malfunction by being inoperable until the next power is turned on after a predetermined output is generated, ensures reliable operation, and facilitates the integration of an electronic control circuit.

An embodiment of the present invention will be described below with reference to the drawings.

Although the embodiment will be described assuming that recording/playback is performed while the tape deck is not available in combination with a timer that turns on the power, the mode control circuit according to the present invention does not need to be combined with a timer; It is also possible to create a function that allows you to enter play mode simply by pressing the button.

FIG. 1 shows an embodiment according to the present invention, in which a first flip-flop circuit 1 (hereinafter simply referred to as FFl) is set by a mode selection signal ■ and a first flip-flop circuit 1 is set by a signal J indicating establishment of a predetermined mode. The second flip-flop circuit 2 (hereinafter simply referred to as FF2) comprises a second flip-flop circuit 2 (hereinafter simply referred to as FF2).

The mode selection signal I is applied to the set input edge 1 of FFl, the power-on reset signal K is applied to the first reset input R1, and the output Q2 of FF2 is applied to the second reset input edge R2 of FFl. It is now possible to

The output Q□ of FF1 generates an output signal instructing a predetermined mode setting.

A signal J indicating establishment of a predetermined mode is applied to the set input terminal S2 of FF2, a reset signal K at power-on is applied to the reset input terminal R3, and the output Q2 is the reset input of FF1 as described above. It is added to end R2.

The power-on reset signal is generated by a time constant circuit 3 consisting of a capacitor and a resistor when the power is turned on.

Next, the operation of the circuit configured as described above will be explained with reference to the timing chart shown in FIG.

At the same time as the power is turned on (time i in the figure), the mode selection signal I becomes a high level H as shown in Figure 2g, and when the power is turned on, the initialization signal is sent from the time constant circuit 3 as shown in Figure 2A. Output Q of generation, FF1, and FF2
l? The output Q2 becomes a high level H as shown at A' and A'' in Fig. 2 f1 and Fig. 2 i.

The system enters the state at time ii in FIG. 2, at which point the system reset ends.

When the mode selection signal I is generated at the time B in FIG. 2g, that is, at time iii in the figure, and changes from high level H to low level L, the set input terminal S□ of FF1 is The set level, that is, the low level L is reached at the position shown in C, and the output Q1 of the FF1 changes to the low level L at the position D in FIG. 2f.

This low level L signal is applied to an electronic control circuit (not shown) to set the tape deck, for example, in a play mode or a recording play mode.

After a predetermined delay time including mechanical transition time, the signal J indicating that the tape recorder has transitioned to the specified mode is F.
The set signal of F2 becomes low level L at the position E in FIG. 2g, and is applied as a set signal to the set terminal S2 of FF2.

The signal J may be, for example, a signal obtained by mechanically detecting that the operation button of the tape deck has been moved, or a signal obtained by detecting that the tape speed has reached a constant speed value.

This signal sets FF2, and the output Q2 of FF2 changes from a high level H to a low level L as shown in F in FIG. 2g, and as a result, FF1 is reset as shown in G in FIG. 2e. The output Q1 of FFl changes from low level L to Fig. 2 f.
It returns to the high level H as shown in M of FIG.

In this state, the output Q1 of FFl is fixed at a high level H1, and the output Q2 of FF2 is fixed at a low level L, so even if the mode selection signal I changes and the set signal of FF1 is input again, the output Q1 of FFl remains unchanged. No changes occur and there is no risk of malfunction.

Should you turn on the power again? yF2 is reset and the above operation is performed.

As described above, according to the present invention, the mode control circuit is fixed in an operation inhibited state until the power is turned on again by feeding back the signal generated when a predetermined mode is established, so that it operates only when the power is turned on. There is no risk of malfunction.

Furthermore, since it is composed only of logic gates, it does not operate unstable like a differential circuit, and operates reliably, making it easy to integrate the control circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of a mode control circuit according to the present invention, and FIG. 2 is a timing chart of the main parts in FIG. 1. 1...First flip-flop circuit, 2...
...Second flip-flop circuit, Sl...Set input terminal of first flip-flop circuit, R construction...
・First reset input terminal of the first flip-flop circuit, R2... Second reset input terminal of the first flip-flop circuit, S2... Second reset input terminal of the second flip-flop circuit Set input terminal, R3...Reset input terminal of the second flip-flop circuit.

Claims (1)

[Claims for Utility Model Registration] 1. A first flip-flop circuit that controls the controlled device to be in a predetermined mode by inverting to the set state by inputting a mode selection signal after inputting a reset signal; By inputting a signal that is generated when the controlled device enters a predetermined mode while being reset by a reset signal, the device is inverted to the set state, and this output puts the first flip-flop circuit in the reset state. 1
a second flip-flop circuit that inhibits the flip-flop circuit from returning to the set state by the mode selection signal; 2. The mode control circuit according to claim 1, wherein the reset signal is activated upon power-on of the controlled device.