JPH039141Y2 - - Google Patents

Description

[Detailed explanation of the invention] This invention does not require a differential circuit using CR,
The present invention also relates to a timer standby circuit that can have one terminal when integrated.

In recent years, with the rapid development of electronic technology, tape decks have come to be controlled in various modes by integrated deck control circuits. This integrated deck control circuit momentarily closes the stop, play, fast forward, rewind, record, and pause switches, which are configured by non-lock type switches connected to each mode terminal. Therefore, the operation corresponding to the operation mode switch can be automatically obtained. And if you have such a deck control circuit,
In order to easily control the mode, a timer standby circuit is provided which performs recording or playback at a desired time in combination with a timer circuit.

FIG. 1 is a circuit diagram showing an example of a deck control circuit having a timer standby circuit commonly used in the past. When any of the mode switches MS1 to MS6 is closed and the corresponding input terminals IN1 to IN6 go to "H" level, the deck controller A switches the head base movement mode (not shown) to the "H" level. Activate the solenoid and mode to set the corresponding mode. On the other hand, the timer standby circuit includes a capacitor C1 and a resistor R1 that differentiate the rising edge of the power supply +B, and the differential output is sent to the playback input terminal IN2 and the recording input terminal IN5 of the deck controller A via diodes D1 and D2 for preventing backflow. It is composed of a timer mode select switch SW that selectively supplies the timer mode.
Then, a contact point of a timer circuit (not shown) is provided in the path of the power supply +B, and when the contact point is closed when a predetermined time has elapsed, the power supply +B is supplied and the differential circuit consisting of the capacitor C1 and the resistor R1 is activated. A differential pulse is generated when the power supply +B rises. This differential pulse is configured to trigger the playback input terminal IN2 or the recording input terminal IN5 of the deck controller A via the diodes D1 and D2 selected by the timer mode select switch SW. However, the timer standby circuit with the above configuration,
Since the initial reset of the deck controller A is performed by the output of the integrating circuit made up of the resistor _R2 and the capacitor _C2 , which is activated when the power supply +B rises, it is necessary to generate a differential pulse that is longer than this reset period. be. However, the output pulse width of the CR-based differentiating circuit varies greatly depending on various conditions, and as a result, control by the timer standby circuit becomes uncertain. Further, since the differentiating circuit requires a capacitor, the circuit is not suitable for integration, and a large number of capacitors are required to obtain a wide differential pulse.

Therefore, the purpose of this invention is to provide a timer standby circuit that does not require a differential circuit using a CR, can operate reliably, and can have only one terminal when integrated. . Hereinafter, the timer standby circuit according to this invention will be explained in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the deck controller to which the timer standby circuit according to the invention is applied, and the deck controller A is
Mode switch MS1 for playback and recording mode is connected between mode input terminals IN1 and IN2 and ground.
MS2 is provided. Furthermore, pull-up resistors R1 and R2 are connected between the mode input terminals IN1 and IN2 and the power supply +B, respectively. B
is a deck mechanism, and the mechanical mode is switched under the control of a deck controller A. In this case, deck mechanism B operates a solenoid in response to the output of deck controller A to move the head base to the operating mode position and drive the motor. Furthermore, when the deck mechanism B moves to the operation mode, it sends out an "H" level operation confirmation signal X from the output OUT. P is an inverter that inverts the operation confirmation signal X, M is an operation memory circuit, and two INV.OR
The combination of gates G1 and G2 forms a generally well-known latch circuit configuration, which uses the output of inverter P as a set input and is reset by a reset signal. Q is a transistor whose base input is the output of the memory circuit M via a resistor R3, and whose emitter is connected to ground. SW is a timer standby switch, and the playback and recording input terminal IN1 of the deck controller A is connected to fixed ends c and e by a movable piece b connected to a common terminal a.
and IN2 are selected and supplied to transistor Q.

In the timer standby circuit configured in this way, when the power +B is supplied, the movable piece b of the timer standby switch SW
For example, when the mode switch SW1 is momentarily closed in the off mode state by connecting it to the fixed contact d, the deck controller A controls the deck mechanism B to the regeneration mode because the input terminal IN is dropped to the "L" level. . Further, by momentarily closing the mode switch SW2, the deck controller A controls the deck mechanism B to the recording mode, and normal mode control is performed.

Next, the timer mode will be explained. first,
When a timer-controlled contact (not shown) connected to the path of power supply +B is closed, power supply +B is connected to the third
It stands up as shown in Figure a. When power supply +B comes on,
An initial reset circuit (not shown) is activated,
The deck controller A is reset by being supplied with a reset signal (FIG. 3b) which remains at the "L" level only for a certain period of time from the rise of the power supply +B. In addition, a reset signal is sent to the memory circuit M having a latch circuit configuration using INV.OR gates G1 and G2.
When RST is supplied, since the set signal supplied from inverter P is at the "H" level as shown in FIG. 3c, it is reset and its output becomes "H" as shown in FIG. 3d. ” becomes.

When the output of the memory circuit M becomes "H", the transistor Q1 is turned on and its collector potential becomes "L" level as shown in FIG. 3e. In this case, if the movable piece b of the timer mode switch SW selects the fixed contact c as shown, for example, when the transistor Q is turned on, the input terminal IN1 of the deck controller A is grounded. As a result, the deck controller A operates in the same manner as when the mode switch MS1 is turned on, and controls the deck mechanism B to the regeneration mode. The deck mechanism B switches modes in response to the output of the deck controller A to move the head base and drive the motor. Then, this decking mechanism B generates an operation confirmation signal X when the operation is completed. When the operation confirmation signal X is generated, time t is shown in FIG. 3c.
As shown by 1, the output of the inverter P is inverted from "H" to "L". As a result, since the memory circuit M is set by the "L" level output of the inverter P, its output is inverted to the "L" level as shown in FIG. 3d. When the output of the memory circuit M goes to "L" level, the transistor Q turns off, so the input terminal IN of the deck controller A
1 is returned to the "H" level by the pull-up resistor R1, and the reproduction state continues to be maintained. In this case, once the latch circuit is set by INV.OR gates G1 and G2, it will not be able to output the reset signal again.
Since it is not reset unless RST is supplied, the timer operates only once when the power is turned on, and its operation is reliable.

In the above embodiment, a case has been described in which the memory circuit M is constituted by a latch circuit, but the invention is not limited to this.
For example, as shown in Figure 4, the flip-flop FF
It may also be configured by In this case, power +
B is supplied to the D input, an operation confirmation signal X is supplied to the clock input CK, a reset signal is supplied to the clear input CL, and a reset output is supplied to the base of the transistor Q via the resistor R3.
Further, in the above embodiment, the operation confirmation signal The output may be generated continuously.

As explained above, the timer standby circuit of this invention forms a closed loop using the operation confirmation signal output from the deck mechanism without using the CR time-fixing circuit, so the timer operation does not occur when the power is turned on. The operation is extremely reliable. Furthermore, this invention is suitable for integration because it does not use a time-limiting circuit based on CR. Furthermore, this invention has various excellent effects such as requiring only one external terminal when integrated.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional timer standby circuit, Fig. 2 is a circuit diagram showing an embodiment of the timer standby circuit according to this invention, and Figs. 3 a to e.
2 is an operational waveform diagram of each part of the circuit shown in FIG. 2, and FIG. 4 is a circuit diagram showing another embodiment of the memory circuit shown in FIG. 2. A...Deck controller, B...Deck mechanism, MS1, MS2...Mode switch, M...
Memory circuit, SW...Timer standby switch, Q...Transistor, G1, G2...INV.
OR gate, P... Inverter, R1~R3...
Resistance, FF... flip-flop.

Claims (1)

[Scope of utility model registration request] An operation detection section that sends out an operation confirmation signal when the tape deck is in operation, and a storage circuit that is reset by an initial reset signal when the power is turned on and set by an operation confirmation signal output from the operation detection section are provided. A timer standby circuit characterized in that the tape deck is configured to control a tape deck in a predetermined mode by the output of the memory circuit when the power is turned on.