JPS5843020A - Resetting circuit of logical device - Google Patents

Abstract

PURPOSE:To restart simultaneously all related logical circuits from an initial state, by resetting simultaneously these related logical circuits if one of the logical circuits has a fault. CONSTITUTION:The logical circuits 11-13 which are related to each other have pulse output terminals TF and reset terminals RE, respectively. The fault detecting circuits 21-23 are connected to the terminals TF. When either one of these circuits 21-23 detects a fault, the circuits 11-13 are reset. In this connection, a reset signal producing circuit 11 is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION This Ii&@ relates to a reset signal for a logic device consisting of a plurality of m, 1 mg 1 paths that falsely display the terminal for outputting the KFi pulse signal during normal operation and the reset terminal for initializing the operation, respectively. It is something.

Conventionally, a device having a plurality of logical maw paths is equipped with an individual 0 logical 1 m-path K111 pattern detection circuit, which detects abnormal operation of the logical m direction path and selects only the corresponding maw path. It was structured like this. However, each logic circuit must be operated in conjunction with other logic circuits! Due to this, the re-installation procedure after setting KF19 to restore the normal operation of the device (KJ:j)
It is essential to know the operating state before a failure occurs in a logical circuit! But nine. This rounding control becomes complicated, and the amount of programming increases in the logic circuit of the four-dumb control.

ζt）l＠＠In order to solve the above-mentioned drawbacks, the IIIg & fault detection circuit is configured so that even if one oiwtm circuit becomes abnormal, multiple related logic m circuits are simultaneously removed. 9 sets of movements, these are the ones with a fighting spirit.
The ia road is in the initial state, and the movement is repeated simultaneously, *ym*s
This eliminates the need for development costs.

FIG. 1 shows an example of the present invention, in which logic circuits 11 @ II and 1. are connected to the pulse output terminal TF and the reset terminal Rgt, respectively. The pulse output terminal TFtj outputs a pulse train for a period of time when its logic 1 path operates normally, and in 90 cases, the output pulse is always at a high level "H" KTol in the period TI (for example, IQms). The low level is 1L1 when I<the pulse width T (for example, S#$).

When the reset terminal RBK is given a low level, the logic circuit is reset, and at that time, the pulse output terminal TP of the logic circuit becomes a high level ""H". After that, when the reset terminal RB becomes a high level @H', the logic circuit is reset. The logic circuit is initialized and starts operating.

Pulse output terminal T1 of each logic circuit l, ~II! Fault detection circuits 21 to 2- are respectively connected to the terminals. These failure detection H paths 2. ~2. When the input pulse Fi disappears, this is detected, and in this example, the monostable multivibrators s1 to 3. The output of the pulse output terminal TF corresponding to the input terminal DK of the multi-by-play is applied, and it is triggered at the rising edge of the input terminal DK, and a constant width I(
Output the route.

The width T of each output pulse of these monostable multivibrators 31 to 3 is the output of the pulse output terminal T
! l J19j T Longer than 1, for example, set to 49m5.

These failure detection paths 2□~2. For example, if a fault is detected in any of the related logic circuits 1. ~1- is reset. For this reason, a reset signal generation circuit 11 is provided. The reset signal generation circuit 11 is connected to the fault detection circuits 2m to 2.
．． Monostable multivibrator 41~
4. , these monostable multivibrators 4. ~
4. Input terminals of DK monostable i multi-viprator 31-3
A Q output of - is given, and it is triggered at the rising edge and outputs a relatively short pulse of one foot width, for example, 1 ms.

These monostable multivibrators4. ~4. Each Q output of is connected to an npn transistor 5°~ through a resistor gate tube.
5. are supplied to each base. These transistors
5.9, 7'' is grounded, 1°''' is wired-to-wire connected to 1, and logic circuits 11 to 1. Each reset terminal REK@
is connected to the positive galvanic terminal 1 through the resistor 12.
．． Connected to 3.

The connection point between the resistor 12 and the collector traces back the collector emitter of the transistor 14 and is grounded.
- This is for generating an initial reset signal when starting up this transistor 121, and the output of the power-on reset generation circuit 15 is applied to the pace of the transistor 14 through the input I (-16). 15, the power supply terminal 13 is grounded through the resistor 17 and the capacitor 18, and the connection point between the resistor !#17 and the capacitor 18 is connected to the circuit 15.
The output signal is supplied to the in-bark 16 as an output.

Monobun star multivibrator 31-3. The circuit is designed to be able to retrigger from 41 to 4 degrees, and for a single pulse as shown in Figure 2A, it is triggered in advance by the rising edge of the input at the input terminal as shown in Figure 2 13. Outputs a pulse with the specified time width. The Q output of these multivibrators is 10" between their pulse outputs JtJf,
The Q output is its inverted output. The terminal input is as shown in Figure 3A.
As shown in the figure, the length of the pulse train is longer than the output pulse width p.
- If Mi is active, it is re-triggered at the rising edge of each input pulse, and when the pulse input stops for a set time or more, the output returns to its original state as shown in #I3 diagram BK.

Theory fmH path 1. Figure 1 shows an example in which a reset is applied repeatedly until restart when a failure is detected. 1 Failure detection circuit 2. 1m circuit in a circle 1. The logical product of the output of the pulse output terminal TF and the output of the reset signal generating circuit 11 is obtained by the t-AND circuit 19, and the output is given to the input terminal of the single Aken multi-vibrator 3m. , sea urchin.

Resetting this invention in various modes below (b)
The operation of the road will be explained.・＾ When the power is turned on, the output of the PR is as shown in FIG. 4A. When the power is turned on at time t1, the output of the power-on reset generating circuit 15 shown in FIG. 1 rises in an integral waveform. The output of circuit 15 is -
When the potential is exceeded, at time t-, the output of the inverter 16 goes to a low level "L" as shown in FIG. 4B, changing the transistor 14 from a conductive state to a cut-off state. On the other hand, when the power is turned on, the monostable multivibrator quadruple ~
4. Transistors 51 to 5 at each output light low level 6L"
1 level is cut off. Therefore, the output of the reset signal generator 11 is at a low level @L as shown in Figure 4C.
From i level/H'KR, -1 road 11~1. - Operate all at once from the reset pattern embroidery. As a result, the circuit circuit 1, for example, sends out a pulse train from its terminal TF as shown in Figure 4, and 41! The output of the detection circuit 2□ becomes a low level "L" as shown in Fig. 4 BK, and the output of the single tube f multivibrator 4□ is stored as a low level 1LM as shown in Fig. 4 12. Ru.

B - When the operation of the platform circuit 11 stops - The circuit 1 stops operating and no pulses are sent to the output terminal TF from time t4 as shown in FIG.

It becomes. As a result, the failure detection circuit 2. As shown in the fifth factor B, the metastable multivibrator 31 in
After (D #IL" * K II, its crystal force 4 becomes a high level @kl". This triggers the stable multivibrator 4, and its output Qrj 5.
As shown in the figure OK, the high level becomes "H" for time T4.

During this period, the transistor 51 becomes conductive, and as shown in Figure 5, the reset signal generation circuit 1 goes to a low level 1L'' for that time T4, and then becomes a high level ``H'' again. Therefore, all logic circuits l , ~1. is reset,
Starts operation from the old initial state.

When the above reset operation is completed normally, a pulse train is sent out again from the pulse output terminal TF and the fault detection circuit 2
As shown in the fifth factor B, the output of 1 collapses at time t and becomes vector 1L'', resulting in a normal operating mode. However, if the reset operation is not performed normally and there is only one sword, the failure detection circuit 2 ．．
The output of is held at a high level @H#, and the restart operation of circuit l is no longer performed.

C logic circuit 1. As shown in the sixth EAIIC, logic circuit 1. At point 1, stop working. When Palko is no longer output, note 5N11
Similarly to the operation for 1°, as shown in the sixth factor BK, the output of the lIJ harm detection circuit 2 is generated, and the output of the monostable multivibrator 4m is generated as shown in No. 61C. Then, a reset pulse is generated as shown in the sixth diagram. Monostable Multivibrator 4.0 The input is given the output of the pulse output terminal TV and the product of the reset pulse.At the rising edge of the rounding reset pulse, the monostable multipipe, the regulator 3. is triggered and its output becomes a low level @L1 as shown at time t of factor 6 B. Therefore, if the reset operation is not performed normally, the sixth cause B occurs when the multivibrator 3. When it returns, the same reset operation as above is repeated again.

In addition#! At 1-, monostable multivibrator 41~
4.0 output cover transistor5. ~5. Although the structure is configured to use a wired-or-width method via a porcelain gate, it is also possible to configure it using a porcelain gate.

As explained above, according to this invention, trouble detection 1 is easy.
It is possible to reset multiple logic circuits all at once. %, there is little demand for the ability to restore the operation before the failure even in the event of a failure, so the invention that allows the system to be reset with a simple configuration is of great significance.

This is shown in case B above, and according to Kuu-ro, there is no effect on system operation! ! If the circuit cannot be reset to - and cannot return to 1, it is possible to disconnect the L circuit and continue operation.On the other hand, according to the nine circuits shown in case C above, the logic circuit essential for system operation Resetting is performed repeatedly until the normal operation of company #C begins.In this way, Jin's invention allows these reset circuits to be configured according to the weight of the circuit.

[Brief explanation of drawings]

Fig. 1 is a logic circuit diagram showing an embodiment of the present invention, Figs. 2 and 3 are timing diagrams showing the operation of a monostable multivibrator, and Fig. m4 is a timing diagram showing the operation when the power is turned on. FIGS. 5 and 6 are operation timing diagrams when the logic circuit stops, respectively. 1, ~1. : Theory m circuit, 21-2. :lllll small detection circuit, ~3. ,4. ~Oil: Monostable multivibrator, 11: Reset signal generation circuit, 15: Power-on reset generation circuit, TF: Pulse output terminal, RE: Reset terminal. Patent owner Nippon Telegraph and Telephone Public Corporation agent Single Needle Taku! 11＼ Fang 1 Figure

Claims (1)

[Claims] (1) A logic device consisting of a plurality of logic paths, each having a 9-set koji to initialize the operation and a pulse output terminal that periodically outputs a pulse signal during normal operation.
Regarding C, each of the above! A fault detection circuit outputs a detection signal when the pulse signal is not output for a certain period of time or more at each pulse output terminal of one circuit, and the outputs of these detection circuits 1lIIKIII! , and when at least one of the detection signals is input, a reset pulse is generated and the seven pulses are applied to all of the above circuits (C)9.
- a reset signal seller circuit for supplying a reset signal to a terminal terminal;