JP2550689B2 - Reset circuit - Google Patents
Reset circuitInfo
- Publication number
- JP2550689B2 JP2550689B2 JP64000672A JP67289A JP2550689B2 JP 2550689 B2 JP2550689 B2 JP 2550689B2 JP 64000672 A JP64000672 A JP 64000672A JP 67289 A JP67289 A JP 67289A JP 2550689 B2 JP2550689 B2 JP 2550689B2
- Authority
- JP
- Japan
- Prior art keywords
- reset
- circuit
- test
- test mode
- mode signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路のリセットに関し、特にシス
テムクロックの分周回路のリセット回路に関する。The present invention relates to reset of a semiconductor integrated circuit, and more particularly to a reset circuit of a system clock divider circuit.
従来、半導体集積回路の発振器と分周回路からなるシ
ステムクロック発生回路はリセット回路が接続されてお
らず、テスト時に分周回路をリセットして初期値をユニ
ークに決められなかった。Conventionally, a reset circuit is not connected to the system clock generating circuit including the oscillator and the frequency dividing circuit of the semiconductor integrated circuit, and the frequency dividing circuit cannot be reset to uniquely determine the initial value during the test.
このようにテスト時に発振回路をリセットして初期値
をユニークに決められなかったため、LSIテスタ等によ
るテスト時には発振器のマッチングをとるためにテスト
時間が増大し、またテストに使用する外部のハードウェ
アおよびソフトウェアに多くのテクニックやノウハウが
必要であった。Since it was not possible to uniquely determine the initial value by resetting the oscillator circuit during the test in this way, the test time was increased to match the oscillator during the test using an LSI tester, and the external hardware used for the test and The software required a lot of techniques and know-how.
本発明の半導体集積回路のリセット回路は、テスト状
態にあることを示す入力と、リセット入力によりテスト
状態でのみ有効なリセットパルスを生成し、分周回路等
をリセットし、初期状態を決定する。A reset circuit of a semiconductor integrated circuit according to the present invention generates an input indicating a test state and a reset input to generate a reset pulse that is effective only in the test state, resets a frequency divider circuit, and determines an initial state.
次に、本発明を実施例によって説明する。 Next, the present invention will be described with reference to examples.
第１図，第２図は本発明の一実施例である。第１図は
リセット回路部分、第２図は発振器と分周器からなるシ
ステムクロック発生回路部分である。発振回路の分周器
10,11を第３図の様にリセット入力を持つものとし、発
振回路９とリセット回路10,11を接続した。1 and 2 show an embodiment of the present invention. FIG. 1 is a reset circuit portion, and FIG. 2 is a system clock generation circuit portion including an oscillator and a frequency divider. Oscillator circuit divider
Oscillation circuit 9 and reset circuits 10 and 11 were connected to each other, with 10 and 11 having a reset input as shown in FIG.
その結果、第４図の様にテスト状態（▲▼＝
０）でリセット入力（▲▼＝０）があると、
TSRST端子よりワンショットのリセットパルスが出力さ
れ、分周器の出力が“1"から“0"へ変化し、▲
▼信号の立ち下がりエッジで発振器の分周回路がリセ
ットできる。As a result, the test condition (▲ ▼ =
If there is a reset input (▲ ▼ = 0) in 0),
A one-shot reset pulse is output from the TSRST pin, the output of the frequency divider changes from "1" to "0", and
▼ The divider circuit of the oscillator can be reset at the falling edge of the signal.
第５図は本発明の他の実施例である。 FIG. 5 shows another embodiment of the present invention.
テスト状態であることを示すために、通常の使用状態
では考えられない信号を入力（本実施例では▲▼端
子，▲▼端子を同時にロウレベル“0"に設定）する
ことによってテストモードの端子のない半導体集積回路
でも発振器と分周回路とからなるシステムクロック発生
回路をリセットし、クロックの初期状態を決定できる。In order to indicate the test state, by inputting a signal which is not considered in the normal use state (in this embodiment, the ▲ ▼ terminal and the ▲ ▼ terminal are simultaneously set to the low level “0”), the terminal in the test mode is set. Even if there is no semiconductor integrated circuit, the system clock generating circuit including the oscillator and the frequency dividing circuit can be reset to determine the initial state of the clock.
本発明では、半導体集積回路の分周回路をテスト時に
リセットし初期値をユニークに決定できるため、システ
ムクロックとLSIテスタの信号とのマッチングが容易に
実現し、発振器を有する半導体集積回路のテスト時間を
大幅に短縮できテスト時に必要なハードウェアおよびソ
フトウェアを簡略化できる効果がある。In the present invention, since the frequency divider circuit of the semiconductor integrated circuit can be reset at the time of testing to uniquely determine the initial value, matching between the system clock and the signal of the LSI tester can be easily realized, and the test time of the semiconductor integrated circuit having the oscillator can be This has the effect of significantly shortening the hardware and software required during testing.
第１図，第２図，第３図は本発明の半導体集積回路のリ
セット回路の第１の実施例で、第４図は第１の実施例の
タイミングチャート、第５図は他の実施例回路図であ
る。 １……リセット入力、２……テストモード入力、３……
分周回路リセットパルス、４……発振器入力、５……CG
出力、６……分周器出力、７……発振器出力、８……分
周器入力、９……分周器出力、10……分周器リセット入
力。1, 2 and 3 show a first embodiment of a reset circuit for a semiconductor integrated circuit according to the present invention, FIG. 4 is a timing chart of the first embodiment, and FIG. 5 is another embodiment. It is a circuit diagram. 1 …… Reset input, 2 …… Test mode input, 3 ……
Frequency divider reset pulse, 4 ... Oscillator input, 5 ... CG
Output, 6 ... Divider output, 7 ... Oscillator output, 8 ... Divider input, 9 ... Divider output, 10 ... Divider reset input.
Claims (3)
と、リセット信号およびテストモード信号を受け、前記
テストモード信号がテスト状態を示すレベルにあるとき
に前記リセット信号が入力されたことに応答して前記分
周回路をリセットし初期値を決定させる手段とを備える
ことを特徴とするリセット回路。1. A frequency dividing circuit for generating a system clock, a reset signal and a test mode signal being received, and in response to the input of the reset signal when the test mode signal is at a level indicating a test state. And a means for resetting the frequency dividing circuit to determine an initial value.
から供給されることを特徴とする請求項１記載のリセッ
ト回路。2. The reset circuit according to claim 1, wherein the test mode signal is supplied from a test mode terminal.
いて生成され、これら複数の信号が通常の使用状態では
考えられないレベルのとき前記テストモード信号は前記
テスト状態を示すレベルをとることを特徴とする請求項
１記載のリセット回路。3. The test mode signal is generated by using a plurality of signals, and when the plurality of signals are at a level that is not considered in a normal use state, the test mode signal has a level indicating the test state. The reset circuit according to claim 1, wherein:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP64000672A JP2550689B2 (en) | 1989-01-04 | 1989-01-04 | Reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP64000672A JP2550689B2 (en) | 1989-01-04 | 1989-01-04 | Reset circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02180428A JPH02180428A (en) | 1990-07-13 |
| JP2550689B2 true JP2550689B2 (en) | 1996-11-06 |
Family
ID=11480235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP64000672A Expired - Fee Related JP2550689B2 (en) | 1989-01-04 | 1989-01-04 | Reset circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2550689B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04245314A (en) * | 1991-01-31 | 1992-09-01 | Nec Corp | System clock generating circuit |
| KR100336753B1 (en) * | 1999-08-06 | 2002-05-16 | 박종섭 | State clock generator |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6089937A (en) * | 1983-10-24 | 1985-05-20 | Nec Corp | Integrated circuit device |
-
1989
- 1989-01-04 JP JP64000672A patent/JP2550689B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02180428A (en) | 1990-07-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070822 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080822 Year of fee payment: 12 |
|
| LAPS | Cancellation because of no payment of annual fees |